Abstract: Provided is a burst mode clock data recovery circuit for extracting clock information and data information from transmitted data to process data synchronized with clock. The circuit includes a bit-rate corrector generating an inversed signal at every half cycle of the clock when transition of input data is generated, the inversed signal maintaining a “high” value with respect to a continuous DC input, a first gated-voltage control oscillator connected to the bit-rate corrector in series, the operation thereof being controlled according to the inversed signal, and a bit-rate detector detecting input bit rate from the inversed signal, adjusting a digital code value of a predetermined bit, and controlling an operational frequency of a delay line of the bit-rate corrector and the first gated-voltage control oscillator to be identical to the input bit rate.

Abstract: Provided is a digital duty cycle corrector for a multi-phase clock application which includes a flip-flop receiving a signal having a first clock cycle as an input and generating a reference signal having a cycle twice the first clock cycle, a duty corrector generating a signal having a second clock cycle that is half the cycle of the reference signal, from the reference signal, a duty detector measuring an amount of a duty error of the second clock cycle signal and generating a digital code value to control a duty cycle of the second clock cycle signal becomes 50%, and a phase inverter inverting a phase of the second clock cycle signal by 180° such that a rising edge of the second clock cycle signal is always fixed constantly regardless of a duty cycle correction operation.

Abstract: Provided is a memory system having a multi-drop bus structure. The memory system includes a bus, a memory controller in which a port connected to the bus is terminated by a resistor having a first impedance value, a connector connected to a point having the first impedance value from the memory controller on a bus line, and a memory module connected to the connector. The memory module includes a first load connected to the connector and having the first impedance value, a second load connected to the first load and having a second impedance value, a first chip in which a port connected to the second load is terminated by a resistor having the second impedance value, a via hole penetrating a printed circuit board of the memory module between the first load and the second load, a third load connected to the via hole and having the second impedance value, and a second chip in which a port connected to the third load is terminated by a resistor having the second impedance value.

Abstract: Provided is a dual loop DLL for generating an internal clock signal synchronized with an external clock, which includes a reference DLL receiving a reference clock and generating a plurality of phase clock signals having a first phase difference, a coarse loop selecting one of the phase clock signals and generating first through third digital codes to allow the internal clock signal to have a phase difference smaller than a second phase difference with respect to the external clock, and a fine loop selecting two of the phase clock signals and synchronizing the internal clock signal with the external clock, in response to the first through third digital codes.