Patents Assigned to Postech Foundation and Postech Academy Industry Foundation
  • Patent number: 7817714
    Abstract: Provided is an integrating receiver having an adaptive decision feedback equalizer function and a system having the same. The integrating receiver can simultaneously remove an inter-symbol interference (ISI) and high frequency noises in a high speed DRAM data transmission system. The integrating receiver reduces a probability of wrong decision of data in a state in which the ISI that exists in a channel is removed so as to increase a signal-to-noise ratio (SNR) of a receiver, so that a maximum operation speed increases even in an environment with heavy noises. There is also provided a method of obtaining an equalizer coefficient suitable for the integrating receiver and a method of obtaining a reference voltage by using an integrator in a single ended transmission method. In addition, in order to increase a decision feedback equalizer speed, a look-ahead method is used. In this method, flip flops with a high speed including multiplexers are used.
    Type: Grant
    Filed: January 16, 2007
    Date of Patent: October 19, 2010
    Assignee: Postech Foundation and Postech Academy Industry Foundation
    Inventors: Seung Jun Bae, Hong June Park
  • Publication number: 20100127747
    Abstract: There is provided a digitally controlled oscillator, which is capable of widening its operation range with maintaining its resolution and the maximum frequency at which it operates. The digitally controlled oscillator includes a phase compensation block, a coarse block, and a fine block. The phase compensation block 510 generating a PLL signal PLLCLK and a first clock signal CLK1 which has the same phase and frequency as the PLL signal, in response to a phase control signal DISABLE and a fourth clock signal CLK4. The coarse block 520 generating a second clock signal CLK2 and a third clock signal CLK3 which results from delaying the PLL signal PLLCLK and the first clock signal CLK1 for a given time, in response to a m(integer)-bit coarse A control signal COAR_A and an (m?1)-bit coarse B control signal COAR_B.
    Type: Application
    Filed: February 2, 2009
    Publication date: May 27, 2010
    Applicant: Postech Foundation and Postech Academy Industry Foundation
    Inventors: Kwang Hee CHOI, Hong June PARK
  • Publication number: 20100052539
    Abstract: There is provided a small-sized portable microwave plasma generator capable of generating plasma at atmospheric pressure with low electric power including a coaxial cable, an outer conductor, a connection conductor, and a connection member. The coaxial cable includes a first inner conductor and a dielectric material encircling the first inner conductor. The outer conductor encircles the coaxial cable. The connection conductor includes at least one gas inlet tube. The connection conductor electrically connects between the first inner conductor and the outer conductor at one end of the coaxial cable. The connection member includes a second inner conductor passing through the outer conductor and then connecting to the first inner conductor.
    Type: Application
    Filed: February 4, 2009
    Publication date: March 4, 2010
    Applicant: POSTECH FOUNDATION and POSTECH ACADEMY INDUSTRY FOUNDATION
    Inventors: Jun CHOI, Felipe IZA, Jae Koo LEE
  • Patent number: 7659791
    Abstract: Provided is a guard trace pattern reducing far-end crosstalk and a printed circuit board having the guard trace pattern. The guard trace pattern includes a first guard trace pattern parallel with two signal lines and a plurality of second guard trace patterns perpendicular to the first guard trace pattern to increase mutual capacitance between the two signal lines and the guard trace pattern and increase mutual capacitance between the two signal lines. The printed circuit board includes the aforementioned guard trace pattern disposed between micro strip transmission lines. A characteristic impedance of the guard trace pattern is different from a characteristic impedance of the micro strip transmission lines, and resistances having the same value as a resistance component value of the characteristic impedance of the guard trace pattern are provided to both ends of the guard trace pattern.
    Type: Grant
    Filed: September 5, 2007
    Date of Patent: February 9, 2010
    Assignee: Postech Foundation & Postech Academy Industry Foundation
    Inventors: Hong June Park, Kyoung Ho Lee, Hae Kang Jung
  • Publication number: 20080053694
    Abstract: Provided is a guard trace pattern reducing far-end crosstalk and a printed circuit board having the guard trace pattern. The guard trace pattern includes a first guard trace pattern parallel with two signal lines and a plurality of second guard trace patterns perpendicular to the first guard trace pattern to increase mutual capacitance between the two signal lines and the guard trace pattern and increase mutual capacitance between the two signal lines. The printed circuit board includes the aforementioned guard trace pattern disposed between micro strip transmission lines. A characteristic impedance of the guard trace pattern is different from a characteristic impedance of the micro strip transmission lines, and resistances having the same value as a resistance component value of the characteristic impedance of the guard trace pattern are provided to both ends of the guard trace pattern.
    Type: Application
    Filed: September 5, 2007
    Publication date: March 6, 2008
    Applicant: POSTECH FOUNDATION and POSTECH ACADEMY INDUSTRY FOUNDATION
    Inventors: Hong Park, Kyoung Lee, Hae Jung
  • Publication number: 20070170967
    Abstract: Provided is a multi-phase clock generator which is not influenced by a mismatch and of which a maximum frequency is not limited. The multi-phase clock generator includes a first delay line, a second delay line, a phase detector, and an up/down counter. The first delay line generates a first clock signal by delaying an input clock for a first delay time. The second delay line generates a second clock signal by delaying the input clock for a second delay time in response to a control signal. The phase detector detects a phase difference between the first and second clock signals. The up/down counter generates the control signal in response to an output of the phase detector.
    Type: Application
    Filed: January 22, 2007
    Publication date: July 26, 2007
    Applicant: POSTECH FOUNDATION and POSTECH ACADEMY- INDUSTRY FOUNDATION
    Inventors: Seung Jun BAE, Hong June PARK
  • Publication number: 20070171967
    Abstract: Provided is an integrating receiver having an adaptive decision feedback equalizer function and a system having the same. The integrating receiver can simultaneously remove an inter-symbol interference (ISI) and high frequency noises in a high speed DRAM data transmission system. The integrating receiver reduces a probability of wrong decision of data in a state in which the ISI that exists in a channel is removed so as to increase a signal-to-noise ratio (SNR) of a receiver, so that a maximum operation speed increases even in an environment with heavy noises. There is also provided a method of obtaining an equalizer coefficient suitable for the integrating receiver and a method of obtaining a reference voltage by using an integrator in a single ended transmission method. In addition, in order to increase a decision feedback equalizer speed, a look-ahead method is used. In this method, flip flops with a high speed including multiplexers are used.
    Type: Application
    Filed: January 16, 2007
    Publication date: July 26, 2007
    Applicant: POSTECH FOUNDATION and POSTECH ACADEMY-INDUSTRY FOUNDATION
    Inventors: Seung Jun BAE, Hong June PARK