Patents Assigned to Powdec K.K.
  • Patent number: 12660232
    Abstract: A semiconductor element includes a first semiconductor layer, a second semiconductor layer, a third semiconductor layer, a fourth semiconductor layer, a first intermediate layer, a second intermediate layer, a source electrode, a drain electrode, and a gate electrode. The band gap of the second semiconductor layer is larger than the band gaps of the first semiconductor layer and the third semiconductor layer. The band gaps of the first intermediate layer and the second intermediate layer that sandwich the second semiconductor layer are larger than the band gap of the second semiconductor layer.
    Type: Grant
    Filed: July 6, 2023
    Date of Patent: June 16, 2026
    Assignees: Toyoda Gosei Co., Ltd., Powdec K.K.
    Inventors: Hisao Sato, Koji Okuno, Daisuke Shinoda, Toshiya Uemura, Hironobu Narui, Hiroji Kawai, Shuichi Yagi
  • Patent number: 12520534
    Abstract: This normally-off mode polarization super junction GaN-based field effect transistor has an undoped GaN layer 11, an AlxGa1-xN layer 12 (0<x<1), an island-like undoped GaN layer 13, a p-type GaN layer 14, a p-type InyGa1-yN layer 15 (0<y<1), a gate electrode 16 on the p-type InyGa1-yN layer 15 and a source electrode 17 and a drain electrode 17 on the AlxGa1-xN layer 12. When the polarization charge amount of the hetero-interface between the AlxGa1-xN layer 12 and the undoped GaN layer 11 and the hetero-interface between the AlxGa1-xN layer 12 and the undoped GaN layer 13 is denoted as NPZ and the thickness of the AlxGa1-xN layer 12 is denoted as d, NPZ d?2.64×1014 [cm?2 nm] is satisfied.
    Type: Grant
    Filed: October 5, 2021
    Date of Patent: January 6, 2026
    Assignee: POWDEC K.K.
    Inventors: Hiroji Kawai, Shuichi Yagi, Hironobu Narui
  • Patent number: 12446250
    Abstract: This normally-off mode polarization super junction GaN-based FET has an undoped GaN layer 11, an AlxGa1-xN layer 12, an island-like undoped GaN layer 13, a p-type GaN layer 14 and a p-type InyGa1-yN layer 15 which are stacked in order. The FET has a gate electrode 16 on the uppermost layer, a source electrode 17 and a drain electrode 17 on the AlxGa1-xN layer 12 and a p-type InzGa1-zN layer 19 and a gate electrode 20 which are located beside one end of the undoped GaN layer 13 on the AlxGa1-xN layer 12. The gate electrode 20 may be provided on the p-type InzGa1-zN layer 19 via a gate insulating film.
    Type: Grant
    Filed: September 16, 2021
    Date of Patent: October 14, 2025
    Assignee: POWDEC K.K.
    Inventors: Hiroji Kawai, Shuichi Yagi, Hironobu Narui
  • Patent number: 10014399
    Abstract: This hetero-junction bipolar transistor includes a first n-type GaN layer, an AlxGa1-xN layer (0.1?x?0.5), an undoped GaN layer having a thickness of not less than 20 nm, a Mg-doped p-type GaN layer having a thickness of not less than 100 nm, and a second n-type GaN layer which are sequentially stacked. The first n-type GaN layer and the AlxGa1-xN layer form an emitter, the undoped GaN layer and the p-type GaN layer form a base, and the second n-type GaN layer forms a collector. During non-operation, two-dimensional hole gas is formed in a part of the undoped GaN layer near the hetero interface between the AlxGa1-xN layer and the undoped GaN layer. When the thickness of the p-type GaN layer is b [nm], the hole concentration of the p-type GaN layer is p [cm?3], and the concentration of the two-dimensional hole gas is Ps [cm?2], p×b×10?7+Ps?1×1013 [cm?2] is satisfied.
    Type: Grant
    Filed: February 3, 2017
    Date of Patent: July 3, 2018
    Assignee: Powdec K.K.
    Inventor: Hiroji Kawai
  • Patent number: 9991335
    Abstract: Provided are a semiconductor device and a bidirectional field effect transistor which can easily overcome the tradeoff relation between the high voltage resistance and high speed in the semiconductor device using a polarization super junction, realize both the high voltage resistance and elimination of the occurrence of current collapse, operate at a high speed, and further the loss is low. The semiconductor device comprises a polarization super junction region and a p-electrode contact region. The polarization super junction region comprises an undoped GaN layer 11, an undoped AlxGa1-xN layer 12 with a thickness not smaller than 25 nm and not larger than 47 nm and 0.17?x?0.35, an undoped GaN layer 13 and a p-type GaN layer 14. When the reduced thickness tR is defined as tR=u+v(1+w×10?18) for the thickness u [nm] of the undoped GaN layer 13, the thickness v [nm] and the Mg concentration w [cm?3] of the p-type GaN layer 14, tR?0.864/(x?0.134)+46.0 [nm] is satisfied.
    Type: Grant
    Filed: November 18, 2014
    Date of Patent: June 5, 2018
    Assignee: POWDEC K.K.
    Inventors: Shoko Echigoya, Fumihiko Nakamura, Shuichi Yagi, Souta Matsumoto, Hiroji Kawai
  • Publication number: 20170263710
    Abstract: Provided is a semiconductor element in which a two-dimensional hole gas with an enough concentration can exist, even though the p-type GaN layer is not provided on the topmost surface of the polarization super junction region. The semiconductor element comprises a polarization super junction region comprising an undoped GaN layer 11 with a thickness a [nm] (a is not smaller than 10 nm and not larger than 1000 nm), an AlxGa1-xN layer 12 and an undoped GaN layer 13. The Al composition x and the thickness t [nm] of the AlxGa1-xN layer 12 satisfy the following equation t??(a)x?(a) Where ? is expressed as Log (?)=p0+p1 log (a)+p2{log (a)}2 (p0=7.3295, p1=?3.5599, p2=0.6912) and ? is expressed as ?=p?0+p?1 log (a)+p?2{log (a)}2 (p?0=?3.6509, p?1=1.9445, p?2=?0.3793).
    Type: Application
    Filed: November 5, 2015
    Publication date: September 14, 2017
    Applicant: POWDEC K.K.
    Inventors: Souta MATSUMOTO, Shoko ECHIGOYA, Shuichi YAGI, Fumihiko NAKAMURA, Hiroji KAWAI
  • Patent number: 8785976
    Abstract: A low-loss GaN-based semiconductor device is provided. The semiconductor device has the InzGa1-zN layer (where 0?z<1), the AlxGa1-xN layer (where 0<x<1), the InyGa1-yN layer (where 0?y<1) and the p-type InwGa1-wN layer (where 0?w<1) which are sequentially stacked on a base substrate of a C-plane sapphire substrate, etc. At a non-operating time, the two-dimensional hole gas is formed in the InyGa1-yN layer in the vicinity part of a hetero-interface between the AlxGa1-xN layer and the InyGa1-yN layer, and the two-dimensional electron gas is formed in the InzGa1-zN layer in the vicinity part of a hetero-interface between the InzGa1-zN layer and the AlxGa1-xN layer.
    Type: Grant
    Filed: June 21, 2011
    Date of Patent: July 22, 2014
    Assignees: The University of Sheffield, Powdec K.K.
    Inventors: Akira Nakajima, Sankara Narayanan Ekkanath Madathil, Yasunobu Sumida, Hiroji Kawai
  • Publication number: 20130126942
    Abstract: A low-loss GaN-based semiconductor device is provided. The semiconductor device has the InzGa1-zN layer (where 0?z<1), the AlxGa1-xN layer (where 0<x<1), the InyGa1-yN layer (where 0?y<1) and the p-type InwGa1-wN layer (where 0?w<1) which are sequentially stacked on a base substrate of a C-plane sapphire substrate, etc. At a non-operating time, the two-dimensional hole gas 15 is formed in the InyGa1-yN layer in the vicinity part of a hetero-interface between the AlxGa1-xN layer and the InyGa1-yN layer, and the two-dimensional electron gases is formed in the InzGa1-zN layer in the vicinity part of a hetero-interface between the InzGa1-zN layer and the AlxGa1-xN layer.
    Type: Application
    Filed: June 21, 2011
    Publication date: May 23, 2013
    Applicants: POWDEC K.K., THE UNIVERSITY OF SHEFFIELD
    Inventors: Akira Nakajima, Sankara Narayanan Ekkanath Madathil, Yasunobu Sumida, Hiroji Kawai
  • Patent number: 7368018
    Abstract: A chemical vapor deposition apparatus is provided. The chemical vapor deposition apparatus includes a susceptor support base and a susceptor, and configured to rotate the susceptor with a rotary shaft, a gap as wide as about 1 mm or more is provided along the boundary between the support base and the perimeter of the susceptor to prevent Ga from forming bridges between the support base and the susceptor during growth of III-V compound semiconductors such as GaN, thereby preventing disturbance of rotation.
    Type: Grant
    Filed: July 24, 2002
    Date of Patent: May 6, 2008
    Assignee: Powdec K.K.
    Inventor: Eiichi Yamaguchi