Abstract: A vertical gallium nitride (GaN) field effect transistor (FET) device has a selective area implant region comprising an activated impurity configured from a bottom portion of a recessed region and is substantially free from ion implant damage by using an annealing process. A p-type gate region is configured from the selective area implant region, and the recessed region is characterized by a depth configured to physically separate an n+ type source region and the p-type gate region such that a low reverse leakage gate-source p-n junction is achieved. An extended drain region is configured from a portion of an n-type GaN region underlying the recessed region. An n+ GaN region is formed by epitaxial growth directly overlying the backside region of the GaN substrate.

Abstract: A device comprising a plurality of switches and a plurality of driver units. Each driver unit is coupled to drive a respective switch of the plurality of switches. A system controller is coupled to each of the driver units by a bus, wherein the system controller is configured to coordinate driving of the respective switches by the driver units. The device further comprises at least one communication channel coupled to each of the driver units, wherein the driver units are configured to communicate with each other over the communication channel without mediation by the system controller.

Abstract: A power switching system includes a plurality of power switching units each including a respective power switch, a communication system configured to convey a system-wide switching command to the power switching units along a communication channel, and circuitry, included in each of the power switching units, that is configured to delay execution of the system-wide switching command by a delay.

Abstract: Detecting signals from cascode power devices is described herein. By sensing a gate signal from the high-voltage device, drain waveform characteristics may be monitored. In this manner a power switch may be controlled to avail enhanced performance in a power converter comprising a cascode power device.

Abstract: An ac switch configured to couple and decouple an ac input to a load, the ac switch comprising a first transistor, a second transistor, and a switch controller configured to control the turn ON and turn OFF of the first transistor and the second transistor in response to a request signal. The ac switch comprises an off-state regulator to provide supply regulation to the switch controller in response to the request signal indicating to decouple the ac input to the load and an on-state regulator to provide supply regulation to the switch controller in response to the request signal indicating to couple the ac input to the load. The off-state regulator is configured to provide supply regulation for the switch controller at an extremum of the ac input and the on-state regulator is configured to provide supply regulation for the switch controller at a zero-crossing of the ac input.

Abstract: Vertical gallium nitride (GaN) field effect transistors (FETs) are presented herein. A vertical GaN FET includes cylindrical trench gates arranged in a hexagonal array to form vertical FET channels. At the surface of the vertical GaN FET is a source layer formed in a GaN epitaxial layer and over a GaN substrate. A channel may be formed between the cylindrical gates in the form of a “GaN pillar”; and FET characteristics, including threshold voltage, may be determined, at least in part by a trench nearest neighbor distance. Accordingly, the trench nearest neighbor distance may be selected so that the vertical GaN FET operates as either an enhancement mode or a depletion mode transistor.

Abstract: A method and vertical FET device fabricated in GaN or other suitable material. The device has a selective area implant region comprising an activated impurity configured from a bottom portion of a recessed regions, and substantially free from ion implant damage by using an annealing process. A p-type gate region is configured from the selective area implant region, and each of the recessed regions is characterized by a depth configured to physically separate an n+ type source region and the p-type gate region such that a low reverse leakage gate-source p-n junction is achieved. An extended drain region is configured from a portion of an n-type GaN region underlying the recessed regions. An n+ GaN region is formed by epitaxial growth directly overlying the backside region of the GaN substrate and a backside drain contact region configured from the n+ type GaN region overlying the backside region.

Abstract: The circuits and methods of the present disclosure control the active off-time (high side switch on-time) to ensure the magnetization energy release and resonant capacitor energy release in an asymmetrical half-bridge (AHB) converter finish at the same time and all the stored energy is delivered to the output in each switching cycle. Multiple, parallel, techniques to control the high side switch on-time are illustrated. One is to track the volt-seconds applied during the storage cycle and allow the active release off-time to be limited to the same volt-seconds. A second option is to provide a high side switch on-time that is proportional to the on-time of the low side switch in that switching cycle. A third option is to provide a maximum high side switch on-time that can be programmed to ensure the high side on-time is equal to or smaller than half of the resonant period.

Abstract: A power converter having an integrated input bias self-supply function has an input switch, a controller, an output switch, and an output filter having an inductor. The controller includes control circuitry, a bias drive circuit, and a bias supply circuit. The bias supply circuit includes a bias transistor and a bias diode. The control circuitry and the bias drive circuit produce a bias drive signal indicative of the conductive states of the input and output switches. When the bias drive signal is asserted, the bias transistor is configured to be on and the bias diode is configured to be reverse biased and not conduct any forward current. When the bias drive signal is deasserted, the bias transistor is configured to be off.

Abstract: A half-bridge circuit of a power converter includes a high-side device and a low-side device coupled together at a half-bridge node, which is in turn coupled to a network including an inductor and/or a capacitor. In some examples, the network is a resonant network. The half-bridge circuit further includes a first switch and a second switch. The first switch is coupled between the half-bridge node and a ground reference, in parallel with the low-side device. The second switch is coupled between an input node of the power converter and the half-bridge node, in series with a high-side capacitor that powers a driver of the high-side device. During power-up, the second switch turns on to provide a charging current to the high-side capacitor, while the first switch turns on to augment the charging current by pulling down a voltage at the half-bridge node, thereby diverting a shunt current away from the network.

Abstract: A control system for a power converter having an energy transfer element, a power switch, and a synchronous rectifier (SR). The control system includes an SR control circuit and a cross conduction detector circuit. The detector circuit receives an SR signal indicating whether the synchronous rectifier has been turned on using a drive signal output by the SR control circuit. Based on the SR signal, the detector circuit determines whether the synchronous rectifier is conducting. The detector circuit also compares a voltage at a forward node of the energy transfer element to a threshold voltage to determine whether the power switch is conducting. The detection circuit disables the synchronous rectifier in response to detecting a cross conduction event, based on a determination that the synchronous rectifier and the power switch are both conducting during a time interval in which the synchronous rectifier is turned on.

Abstract: Fast turn-on protection of a cascode switch is presented herein. A cascode circuit includes a depletion mode field effect transistor and an enhancement mode field effect transistor electrically coupled in cascode. During turn-on, a protection circuit detects an overcurrent fault by observing a plateau of a cascode node voltage. An overcurrent fault may be detected in response to the plateau existing for greater than a threshold time duration.

Abstract: A Low Pressure Chemical Vapor Deposition (LPCVD) technique is provided to produce improved dielectric/semiconductor interfaces for GaN-based electronic devices. Using the LPCVD technique, superior interfaces are achieved through the use of elevated deposition temperatures (>700° C.), the use of ammonia to stabilize and clean the GaN surface, and chlorine-containing precursors where reactions with chlorine remove unwanted impurities from the dielectric film and its interface with GaN. The LPCVD silicon nitride films have less hydrogen contamination, higher density, lower buffered-HF etch rates, and lower pin hole density than films produced by other deposition techniques making the LPCVD coatings suitable for device passivation. A metal insulator semiconductor (MIS) structures fabricated with LPCVD SiN on GaN exhibit near ideal capacitance-voltage behavior with both charge accumulation, depletion, and inversion regimes.

Abstract: A lateral surface gate vertical field effect transistor with adjustable output capacitance is described herein. The lateral surface gate vertical field effect transistor includes both a lateral gate and a trench gate. The lateral gate modulates a surface channel and the trench gate includes a controllable depth. The controllable depth may be varied to advantageously adjust output capacitance.

Abstract: A bridgeless power factor correction (PFC) circuit for reducing electromagnetic interference (EMI) is disclosed herein. A current source is placed in parallel with a switch of a low frequency leg. The current source may be turned on during zero crossings of the AC input voltage to limit current and reduce the rate of change in voltage. In turn, EMI may be advantageously reduced without the need for large passive filters or complicated circuitry.

Abstract: A motor driver couples to an auxiliary power supply and to a motor having a winding. The motor driver comprises a first switch and a second switch. The first switch is coupled to the winding at a winding node. The second switch is coupled to the first switch and the auxiliary power supply at an auxiliary node. The auxiliary node corresponds to an output terminal of the first switch and an input terminal of the second switch. The motor driver further comprises control circuitry to place the first switch and the second switch into a first switching configuration in which energy is stored in an inductance of the winding, and a second switching configuration in which the stored energy is delivered to the auxiliary power supply via current through the winding node and the auxiliary node.

Abstract: Magnetic core assemblies include a skewing feature that introduces transverse components into the power flux density vector are disclosed herein. A magnetic core assembly comprises a lower core having a center section and an upper core having a center section. The center sections are aligned to form a center post. A power winding that receives current is wrapped around the center post. The core assembly further comprises a power flux density vector that has transverse and non-transverse components. The transverse components have a higher magnetic reluctance than the non-transverse components. When the assembly is used with a transverse winding, the transverse components from the magnetic core assembly produce a transverse voltage waveform on the transverse winding. The transverse voltage waveform may be observed to detect a change in the sign of the slope of the transverse voltage waveform. The change in the sign of the slope indicates magnetic saturation.

Abstract: Systems and methods for current limit sense compensation for self-charge bias current are described. In one embodiment, a control system for a power converter includes: a branch node coupled to receive a first current from a primary side of an energy transfer element and configured to deliver a main current and a branch current; at least one branch switch coupled to the branch node and configured to receive the branch current; a capacitor coupled to the at least one branch switch, the capacitor being configured to store electrical charge received from the branch current; a first current mirror coupled to the branch node and configured to receive the main current and produce a scaled main current; and a second current mirror coupled to the at least one branch switch and configured to receive the branch current and produce a scaled branch current.

Abstract: Control of a resonant power converter using switch paths during power-up is described herein. During power-up, a first switch path sinks current away from a resonant capacitor while a second switch path sources current to a high-side capacitor. In this way the high-side capacitor may predictably charge to sufficient bootstrap voltage for steady state operation. Additionally, a third switch path may control current to a low-side capacitor.

Abstract: A controller for a power converter includes a primary controller and a secondary controller. The primary controller is coupled to a primary winding of the energy transfer element and a primary switch of the power converter. The secondary controller is coupled to a secondary winding of the energy transfer element and a secondary switch, e.g., a synchronous rectifier, of the power converter. The secondary controller has a synchronous rectifier control/drive circuit, a control logic circuit, and a cross conduction detector circuit. Cross conduction is when the primary switch turns on when the secondary switch is active. The cross-conduction detector circuit produces a Disable SR signal when cross conduction event detected. The cross-conduction detector circuit detects zero voltage switching cross conduction event and a minimum conduction period cross conduction event. The SR drive circuit disables the synchronous rectifier in response to receiving the Disable SR signal.