Abstract: In accordance with the invention a surface mount connector is provided for vertically mounting one circuit device on another. By “vertically mounting” is meant that a circuit device with a major surface is mounted perpendicular to the major surface of another circuit device. The connector is a conductive body comprising a base section and a transverse section, the base section having a width greater than the transverse section and a length which extends beyond the transverse section. Advantageously, the base section extends beyond the transverse section in front, behind and on both sides. In typical use, a major surface of a subassembly can be connected to the transverse section and an edge of the subassembly can be connected to the base extensions. The base can then be connected to the mother board.

Abstract: A system and method is provided for using a serial bus to communicate (either passively or actively) with a point-of-load (“POL”) regulator. Specifically, a power supply controller (“controller”) communicates with at least one POL regulators by writing and/or reading data (either synchronously or asynchronous) over a unidirectional or bi-directional serial bus. In one embodiment of the present invention, the controller is adapted to write initial-configuration data (e.g., output voltage set-point, current limit set-point, etc.) to at least one POL regulator via the serial bus. At least a portion of the initial-configuration data is then used by the POL regulator to produce a particular output. In another embodiment of the invention, each POL regulator includes at least one register for maintaining POL information, such as unique identification information, fault protection information, output voltage set-point data, current limit set-point data, etc.

Abstract: A mounting structure for a semiconductor die that reduces die attach strain within the die attach material without sacrificing the electrical and thermal characteristics of the package. In one embodiment, the mounting structure comprises a die attach metallization layer, a solder mask, and a layer of die attach material. The solder mask forms a solder pattern over the top surface of the die attach metallization layer. The solder pattern covers a portion of the die attach metallization layer to create multiple exposed areas of the die attach metallization layer. Each exposed area is separated by the solder mask and is located under the semiconductor die when the semiconductor die is secured to the mounting structure. A layer of die attach material covers the solder pattern and fills in each one of the exposed areas to form a semiconductor die mounting surface. In another embodiment, the die attach metallization layer is divided into multiple, spaced-apart die attach pads that are electrically coupled together.

Abstract: A packaging system for a high current, low voltage power supply. The power supply uses two bare die field effect transistors whose input and output electrodes are solder attached to low resistance, high current posts in the package. An associated controller chip is mounted to a rigid circuit board, and the circuit board is mechanically attached to the posts. The circuit board thereby gives physical rigidity to the package, but carries no high currents. The use of low resistance, high current posts reduces the heat generated, improving the long term reliability.

Abstract: A semiconductor chip package that includes a DC—DC converter implemented with a land grid array (LGA) package for interconnection and surface mounting to a printed circuit board. The LGA package integrates all required active components of the DC—DC power converter, including a synchronous buck PWM controller, driver circuits, and MOSFET devices. In particular, the LGA package comprises a substrate having a top surface and a bottom surface, with a DC—DC converter provided on the substrate. The DC—DC converter including at least one power silicon die disposed on the top surface of the substrate. A plurality of electrically and thermally conductive pads are provided on the bottom surface of the substrate in electrical communication with the DC—DC converter through respective conductive vias. The plurality of pads include first pads having a first surface area and second pads having a second surface area, the second surface area being substantially larger than the first surface area.

Abstract: A system and method is provided for utilizing output-timing data to control at least one output timing parameter of a point-of-load (“POL”) regulator. Specifically, a power supply controller (“controller”) is adapted to transmit output-timing data to at least one POL regulator. In one embodiment of the present invention, each POL regulator includes an output builder, a control unit and a storage device. The control unit is adapted to store the output-timing data in the storage device. The control unit and the output builder are then adapted to produce an output having at least one output timing parameter in accordance with the output-timing data. Examples of output-timing data include sequencing data, turn-on data, turn-off data, termination data, slew-rate data, etc. For example, a POL regulator may be adapted to utilize output-timing data, or a portion thereof (e.g., slew-rate data), to generate an output having a particular slew rate.

Abstract: A power supply comprises at least one power switch adapted to convey power between input and output terminals of the power supply, and a digital controller adapted to control operation of the at least one power switch responsive to an output measurement of the power supply. The digital controller comprises an analog-to-digital converter providing a digital error signal representing a difference between the output measurement and a reference value, a digital filter providing a digital control output based on a sum of previous error signals and previous control outputs, an error controller adapted to modify operation of the digital filter upon an error condition, and a digital pulse width modulator providing a control signal to the power switch having a pulse width corresponding to the digital control output.

Abstract: An unregulated DC-to-DC power converter suitable for intermediate bus voltage converter applications includes synchronous rectifiers that are driven efficiently to provide faster transition time and reduced loss. The DC-to-DC power converter comprises a transformer having a primary winding and at least first and second secondary windings. An input circuit is coupled to the primary winding and is adapted to apply an alternating polarity square wave voltage to the primary winding. An output circuit comprising an output filter is coupled to a tap of the first secondary winding. The output filter provides a DC output voltage. A first synchronous rectifier is coupled to a first end of the first secondary winding and a second synchronous rectifier is coupled to a second end of the first secondary winding. The second secondary winding has a first end coupled to a control terminal of the first synchronous rectifier and a second end coupled to a control terminal of the second synchronous rectifier.

Abstract: A system and method is provided for dynamically controlling output voltage slew rate in a power converter. Preferred embodiments of the present invention operate in accordance with a power converter including at least a slew-rate control lead (a trim lead, a control lead, etc.), an error-amplifier circuit located therein, a slew-rate circuit, and a controller electrically connected to the power converter and adapted to dynamically control the converter's output voltage slew rate through the transmission of a slew-rate signal. In one embodiment of the present invention, the slew-rate circuit is external to the power converter and electrically connected to both a trim lead of the power converter and to the controller. In another embodiment of the present invention, the slew-rate circuit is internal to the power converter and electrically connected to both a control lead of the power converter and to the error-amplifier circuit.

Abstract: A switched mode power supply comprises at least one power switch adapted to convey power between input and output terminals of the power supply, and a digital controller adapted to control operation of the at least one power switch responsive to an output parameter of the power supply. The digital controller comprises an analog-to-digital converter providing a digital error signal representing a difference between the output parameter and a reference value, a digital filter providing a digital control output based on a sum of current and previous error signals and previous control outputs, the error signals comprising integers having a relatively low numerical range and said control outputs comprising integers having a relatively high numerical range, and a digital pulse width modulator providing a control signal to the power switch having a pulse width corresponding to the digital control output.

Abstract: A pulse width modulation system for use in a switching power supply circuit provides high-resolution pulse width modulated signals. The pulse width modulation system is configured to receive a control signal comprising a (m+n)-bit binary word and to provide a pulse width modulated signal with a predetermined average duty cycle having a resolution of substantially 2−(m+n). The pulse width modulation system includes a timing circuit for providing 2m timing signals, a dithering circuit, and a signal generator. Upon receiving the control signal, the dithering circuit is configured to provide a modified control signal, which comprises a series of up to 2n m-bit binary words. The signal generator is configured to receive the timing signals and the modified control signal and to provide the pulse width modulated signal having a duty cycle, which, when averaged over 2n timing cycles, is approximately equal to the predetermined average duty cycle.

Abstract: The invention provides a subassembly to facilitate co-planar vertical surface mounting of subassembly boards. By “vertically mounting” is meant that a subassembly circuit board with a major surface is mounted perpendicular to the major surface of a circuit motherboard. In accordance with the invention, a subassembly for co-planar vertical surface mounting comprises a subassembly board coupled between a pair of base headers. Advantageously one base header comprises a plurality of mounting lugs secured to a transverse element in a co-planar configuration. The other base header conveniently comprises a plurality of connector pins secured to an elongated header element in co-planar configuration. The two headers interlock with the board to provide connection and co-planar support. A pickup cap attached at the board edge opposite the base permits pick-and-place positioning of the subassembly by conventional equipment without the need for special grippers.

Abstract: A mounting structure for a semiconductor die that reduces die attach strain within the die attach material without sacrificing the electrical and thermal characteristics of the package. In one embodiment, the mounting structure comprises a die attach metallization layer, a solder mask, and a layer of die attach material. The solder mask forms a solder pattern over the top surface of the die attach metallization layer. The solder pattern covers a portion of the die attach metallization layer to create multiple exposed areas of the die attach metallization layer. Each exposed area is separated by the solder mask and is located under the semiconductor die when the semiconductor die is secured to the mounting structure. A layer of die attach material covers the solder pattern and fills in each one of the exposed areas to form a semiconductor die mounting surface. In another embodiment, the die attach metallization layer is divided into multiple, spaced-apart die attach pads that are electrically coupled together.

Abstract: A semiconductor chip package that includes a DC-DC converter implemented with a land grid array for interconnection and surface mounting to a printed circuit board. The package includes a two layer substrate comprising a top surface and a bottom surface. At least one via array extends through the substrate. Each via in a via array includes a first end that is proximate to the top surface of the substrate and a second end that is proximate to the bottom surface of the substrate. At least one die attach pad is mounted on the top surface of the substrate and is electrically and thermally coupled to the via array. The DC-DC converter includes at least one power semiconductor die having a bottom surface that forms an electrode. The power semiconductor die is mounted on a die attach pad such that the bottom surface of the die is in electrical contact with the die attach pad. The bottom of the package forms a land grid array.

Abstract: A power supply comprises at least one power switch adapted to convey power between input and output terminals of the power supply, and a digital controller adapted to control operation of the at least one power switch responsive to an output measurement of the power supply. The digital controller comprises an analog-to-digital converter providing a digital error signal representing a voltage difference between the output measurement and a reference value, a digital filter providing a digital control output based on a sum of previous error signals and previous control outputs, an error controller adapted to modify operation of the digital filter upon an error condition, and a digital pulse width modulator providing a control signal to the power switch having a pulse width corresponding to the digital control output.

Abstract: A system and method is provided for utilizing output-timing data to control at least one output timing parameter of a point-of-load (“POL”) regulator. Specifically, a power supply controller (“controller”) is adapted to transmit output-timing data to at least one POL regulator. In one embodiment of the present invention, each POL regulator includes an output builder, a control unit and a storage device. The control, unit is adapted to store the output-timing data in the storage device. The control unit and the output builder are then adapted to produce an output having at least one output timing parameter in accordance with the output-timing data. Examples of output-timing data include sequencing data, turn-on data, turn-off data, termination data, slew-rate data, etc. For example, a POL regulator may be adapted to utilize output-timing data, or a portion thereof (e.g., slew-rate data), to generate an output having a particular slew rate.

Abstract: A system and method is provided for determining a voltage output of a programmable power converter based on programming voltage data received from one of a variety of alternate sources. Specifically, in one embodiment of the present invention, a control unit is adapted to monitor a digital data serial interface, a digital data parallel interface, and an analog data interface to determine whether programming voltage data has been received. If programming voltage data has been received, the data is used to determine an output voltage for the programmable power converter. If more than one set of programming voltage data has been received, a determination is made as to which set of data takes priority. The selected set of data is then used to determine an output voltage for the programmable power converter.

Abstract: A packaging system for a high current, low voltage power supply. The power supply uses bare die power FETs which are directly mounted to a thermally conductive substrate by a solder attachment made to the drain electrode metallization on the back side of the FETs. The source electrode and gate electrode of each FET are coupled to the circuitry on an overhanging printed circuit board, using CSP solder balls affixed to the front side of the FET die. The heat generated by the FETs is effectively dissipated by the close coupling of the FETs to the thermally conductive underlying substrate.

Abstract: A switched mode power supply comprises at least one power switch adapted to convey power between input and output terminals of the power supply, and a digital controller adapted to control operation of the at least one power switch responsive to an output parameter of the power supply. The digital controller comprises an analog-to-digital converter providing a digital error signal representing a difference between the output parameter and a reference value, a digital filter providing a digital control output based on a sum of current and previous error signals and previous control outputs, the error signals comprising integers having a relatively low numerical range and said control outputs comprising integers having a relatively high numerical range, and a digital pulse width modulator providing a control signal to the power switch having a pulse width corresponding to the digital control output.

Abstract: A power supply comprises at least one power switch adapted to convey power between input and output terminals of the power supply, and a digital controller adapted to control operation of the at least one power switch responsive to an output measurement of the power supply. The digital controller comprises an analog-to-digital converter providing a digital error signal representing a difference between the output measurement and a reference value, a digital filter providing a digital control output based on a sum of previous error signals and previous control outputs, an error controller adapted to modify operation of the digital filter upon an error condition, and a digital pulse width modulator providing a control signal to the power switch having a pulse width corresponding to the digital control output.