Abstract: A power supply module has a printed circuit board (PCB) containing a plurality of electrical components for converting an input voltage to an output voltage. A heat sink is formed over substantially an entire surface area of the PCB for providing heat dissipation. The heat sink is made with a thermally conductive and electrically insulating polymer compound, such as liquid crystalline polymer or polyphenylene sulfide, which is injection molded to surface of the PCB. The heat sink can be formed on a front side and backside of the PCB and may have a plurality of posts for increasing the heat dissipating surface area of the heat sink. By disposing the heat sink over substantially the entire surface of the PCB, the heat sink is able to remove more heat and allow the power supply module to provide more output load current given the same physical size and ambient conditions.

Abstract: A junction field effect transistor (JFET) has a gate region, drain region, and a source region. An epitaxial region having a first conductivity type is disposed over the drain region. The first conductivity type is N-type semiconductor material. The gate region is disposed within a trench which is formed in the epitaxial region. A P+ region is disposed within the epitaxial region and under the gate region. The P+ region has a first doping concentration of a second conductivity type opposite the first conductivity type. A P? region is disposed under the P+ region. The P? region has a second doping concentration of the second conductivity type which is less than the first doping concentration. The P? region may be disposed adjacent to a first portion of the P+ region while another P? region is disposed adjacent to a second portion of the P+ region. The P+ region may be implanted from the gate region deep into the epitaxial region.

Abstract: The electronic circuit breaker comprises an input for connection to a power-supply network and an output for connection to a load. Set between the input and the output are a switch and a limitation block which controls the switch to cause at least partial inhibition thereof in the event of over-current. The circuit breaker further includes a microprocessor connected to the limitation block to inhibit power supply to the load.

Abstract: There is disclosed a power conversion circuit including self synchronous rectifiers and a rapid shutdown section. When power is removed from the power conversion circuit, the rapid shutdown section prevents self oscillation of the self synchronous rectifiers. As a result, power is not drawn from the output and dissipated in the power conversion circuit.

Abstract: A pulse width modulation system for use in a switching power supply circuit provides high-resolution pulse width modulated signals. The pulse width modulation system is configured to receive a control signal comprising a (m+n)-bit binary word and to provide a pulse width modulated signal with a predetermined average duty cycle having a resolution of substantially 2?(m+n). The pulse width modulation system includes a timing circuit for providing 2m timing signals, a dithering circuit, and a signal generator. Upon receiving the control signal, the dithering circuit is configured to provide a modified control signal, which comprises a series of up to 2nm-bit binary words. The signal generator is configured to receive the timing signals and the modified control signal and to provide the pulse width modulated signal having a duty cycle, which, when averaged over 2n timing cycles, is approximately equal to the predetermined average duty cycle.

Abstract: A packaging system for a high current, low voltage power supply. The power supply uses bare die power FETs which are directly mounted to a thermally conductive substrate by a solder attachment made to the drain electrode metallization on the back side of the FETs. The source electrode and gate electrode of each FET are coupled to the circuitry on an overhanging printed circuit board, using CSP solder balls affixed to the front side of the FET die. The heat generated by the FETs is effectively dissipated by the close coupling of the FETs to the thermally conductive underlying substrate. High interconnect densities are achieved through the use of a multilayer printed circuit board. This high interconnect density, with the addition of a magnetic core element, allows the power supply packaging system to incorporate transformer windings for an isolation transformer or an inductor.

Abstract: The invention provides a subassembly to facilitate co-planar vertical surface mounting of subassembly boards. By “vertically mounting” is meant that a subassembly circuit board with a major surface is mounted perpendicular to the major surface of a circuit motherboard. In accordance with the invention, a subassembly for co-planar vertical surface mounting comprises a subassembly board coupled between a pair of base headers. Advantageously one base header comprises a plurality of mounting lugs secured to a transverse element in a co-planar configuration. The other base header conveniently comprises a plurality of connector pins secured to an elongated header element in co-planar configuration. The two headers interlock with the board to provide connection and co-planar support. Edge metallization of the subassembly board can provide enhanced thermal or electrical connection to the underlying portions of one or more lugs.

Abstract: A switched mode voltage regulator has a digital control system that includes dual digital control loops. The voltage regulator comprises at least one power switch adapted to convey power between respective input and output terminals of the voltage regulator and a digital controller adapted to control operation of the power switches responsive to an output of the voltage regulator. The digital controller further comprises dual digital control loops in which a first control loop provides high speed with lower regulation accuracy and a second control loop has high accuracy with lower speed. Thus, the digital control system provides the advantages of both high speed and high regulation accuracy.

Abstract: A packaging system for a high current, low voltage power supply. The power supply uses bare die power FETs which are directly mounted to a thermally conductive substrate by a solder attachment made to the drain electrode metallization on the back side of the FETs. The source electrode and gate electrode of each FET are coupled to the circuitry on an overhanging printed circuit board, using CSP solder balls affixed to the front side of the FET die. The heat generated by the FETs is effectively dissipated by the close coupling of the FETs to the thermally conductive underlying substrate.

Abstract: A system and method is provided for determining a voltage output of a programmable power converter based on programming voltage data received from one of a variety of alternate sources. Specifically, in one embodiment of the present invention, a control unit is adapted to monitor a digital data serial interface, a digital data parallel interface, and an analog data interface to determine whether programming voltage data has been received. If programming voltage data has been received, the data is used to determine an output voltage for the programmable power converter. If more than one set of programming voltage data has been received, a determination is made as to which set of data takes priority. The selected set of data is then used to determine an output voltage for the programmable power converter.

Abstract: A DC-DC power converter has a transformer with a primary side and secondary side. A first power transistor is coupled between a first end of a first winding of the secondary side and a ground terminal. A second power transistor is coupled between a second end of the first winding and the ground terminal. A first driver transistor is coupled to a gate of the first power transistor, and a second driver transistor is coupled to a gate of the second power transistor. A separate driver winding taken off the secondary side of the transformer controls the gates of the first and second driver transistors. First and second inductors are coupled between the opposite ends of the first winding and an output of the power supply. First and second resistors are coupled between the gates of the first and second driver transistors and the ground terminal, respectively.

Abstract: A system and method is provided for utilizing output-timing data to control at least one output timing parameter of a point-of-load (“POL”) regulator. Specifically, a power supply controller (“controller”) is adapted to transmit output-timing data to at least one POL regulator. In one embodiment of the present invention, each POL regulator includes an output builder, a control unit and a storage device. The control unit is adapted to store the output-timing data in the storage device. The control unit and the output builder are then adapted to produce an output having at least one output timing parameter in accordance with the output-timing data. Examples of output-timing data include sequencing data, turn-on data, turn-off data, termination data, slew-rate data, etc. For example, a POL regulator may be adapted to utilize output-timing data, or a portion thereof (e.g., slew-rate data), to generate an output having a particular slew rate.

Abstract: A pulse width modulation system for use in a switching power supply circuit provides high-resolution pulse width modulated signals. The pulse width modulation system is configured to receive a control signal comprising a (m+n)-bit binary word and to provide a pulse width modulated signal with a predetermined average duty cycle having a resolution of substantially 2?(m+n). The pulse width modulation system includes a timing circuit for providing 2m timing signals, a dithering circuit, and a signal generator. Upon receiving the control signal, the dithering circuit is configured to provide a modified control signal, which comprises a series of up to 2n m-bit binary words. The signal generator is configured to receive the timing signals and the modified control signal and to provide the pulse width modulated signal having a duty cycle, which, when averaged over 2n timing cycles, is approximately equal to the predetermined average duty cycle.

Abstract: A semiconductor device has a driver device (10) in proximity to a power device (12). In making the semiconductor device, an N+ layer (24) is formed on a substrate (22). A portion of the N+ layer is removed, substantially down to the substrate, to provide a layer offset (28) between the driver device area and power device area. An epi region of uniform thickness is formed over the driver device and power device areas. A portion of the epi layer is removed to provide another layer offset (70). An oxide layer (68) of uniform thickness is formed over the epi region. The oxide layer is planarized to remove oxide layer over the N+ layer. An oxide-filled trench (80) is formed between the driver device and the power device. The oxide-filled trench extends down to the oxide layer to isolate the driver device from the power device.

Abstract: A system and method is provided for using a point-on-load (“POL”) control unit to program and/or monitor a POL regulator. Specifically, in one embodiment of the present invention, a power supply controller is adapted to provide initial-configuration data to at least one POL regulator. A POL control unit (located within the POL regulator) then stores at least a portion of the initial-configuration data in a storage device and uses at least a portion of the initial-configuration data to produce an output. The POL control unit is further adapted to store fault-monitoring data in the storage device and provide at least a portion of the fault-monitoring data to the controller. If the provided portion violates a known parameter, the controller (or POL control unit) may respond by perform a particular action (e.g., disable the POL regulator, etc.).

Abstract: A semiconductor chip package that includes a DC—DC converter implemented with a land grid array for interconnection and surface mounting to a printed circuit board. The package includes a two layer substrate comprising a top surface and a bottom surface. At least one via array extends through the substrate. Each via in a via array includes a first end that is proximate to the top surface of the substrate and a second end that is proximate to the bottom surface of the substrate. At least one die attach pad is mounted on the top surface of the substrate and is electrically and thermally coupled to the via array. The DC—DC converter includes at least one power semiconductor die having a bottom surface that forms an electrode. The power semiconductor die is mounted on a die attach pad such that the bottom surface of the die is in electrical contact with the die attach pad. The bottom of the package forms a land grid array.

Abstract: The invention provides arrangements to facilitate surface mounting of subassembly boards on a motherboard with reliable, high conductivity interconnection. In accordance with the invention, the subassembly interconnection arrangement is composed of separate power and sense connector arms formed on one or more base headers. The arrangement interconnects and supports the subassembly board on the motherboard surface. Each power arm advantageously comprises a plurality of split-based mounting lugs secured to the arm in a coplanar configuration. Each sense connector arm preferably comprises a plurality of connector pins secured to the arm in a coplanar configuration. Embodiments are disclosed for vertical and horizontal surface mounting.

Abstract: A power supply comprises at least one power switch adapted to convey power between input and output terminals of the power supply, and a digital controller adapted to control operation of the at least one power switch responsive to an output measurement of the power supply. The digital controller comprises an analog-to-digital converter providing a digital error signal representing a voltage difference between the output measurement and a reference value, a digital filter providing a digital control output based on a sum of previous error signals and previous control outputs, an error controller adapted to modify operation of the digital filter upon an error condition, and a digital pulse width modulator providing a control signal to the power switch having a pulse width corresponding to the digital control output.

Abstract: A power control system comprises a plurality of POL regulators, at least one serial data bus operatively connecting the plurality of POL regulators, and a system controller connected to the serial data bus and adapted to send and receive digital data to and from the plurality of POL regulators. The serial data bus further comprises a first data bus carrying programming and control information between the system controller and the plurality of POL regulators. The serial data bus may also include a second data bus carrying fault management information between the system controller and the plurality of POL regulators. The power control may also include a front-end regulator providing an intermediate voltage to the plurality of POL regulators on an intermediate voltage bus.

Abstract: A system and method is provided for dynamically controlling output voltage slew rate in a power converter. Preferred embodiments of the present invention operate in accordance with a power converter including at least a slew-rate control lead (a trim lead, a control lead, etc.), an error-amplifier circuit located therein, a slew-rate circuit, and a controller electrically connected to the power converter and adapted to dynamically control the converter's output voltage slew rate through the transmission of a slew-rate signal. In one embodiment of the present invention, the slew-rate circuit is external to the power converter and electrically connected to both a trim lead of the power converter and to the controller. In another embodiment of the present invention, the slew-rate circuit is internal to the power converter and electrically connected to both a control lead of the power converter and to the error-amplifier circuit.