Patents Assigned to Powerchip Corporation
  • Patent number: 9214242
    Abstract: In a programming method for a NAND flash memory device, a self-boosting scheme is used to eliminate excess electrons in the channel of an inhibit cell string that would otherwise cause programming disturb. The elimination is enabled by applying a negative voltage to word lines connected to the inhibit cell string before boosting the channel, and this leads to bringing high program immunity. A row decoder circuitry to achieve the programming operation and a file system architecture based on the programming scheme to improve the efficiency of file management are also described.
    Type: Grant
    Filed: November 15, 2013
    Date of Patent: December 15, 2015
    Assignees: POWERCHIP CORPORATION, POWERCHIP TECHNOLOGY CORPORATION
    Inventors: Takashi Miida, Riichiro Shirota, Hideki Arakawa, Ching Sung Yang, Tzung Ling Lin
  • Publication number: 20140140129
    Abstract: In a programming method for a NAND flash memory device, a self-boosting scheme is used to eliminate excess electrons in the channel of an inhibit cell string that would otherwise cause programming disturb. The elimination is enabled by applying a negative voltage to word lines connected to the inhibit cell string before boosting the channel, and this leads to bringing high program immunity. A row decoder circuitry to achieve the programming operation and a file system architecture based on the programming scheme to improve the efficiency of file management are also described.
    Type: Application
    Filed: November 15, 2013
    Publication date: May 22, 2014
    Applicants: Powerchip Technology Corporation, Powerchip Corporation
    Inventors: Takashi MIIDA, Riichiro SHIROTA, Hideki ARAKAWA, Ching Sung YANG, Tzung Ling LIN
  • Patent number: 8599614
    Abstract: In a programming method for a NAND flash memory device, a self-boosting scheme is used to eliminate excess electrons in the channel of an inhibit cell string that would otherwise cause programming disturb. The elimination is enabled by applying a negative voltage to word lines connected to the inhibit cell string before boosting the channel, and this leads to bringing high program immunity. A row decoder circuitry to achieve the programming operation and a file system architecture based on the programming scheme to improve the efficiency of file management are also described.
    Type: Grant
    Filed: April 30, 2009
    Date of Patent: December 3, 2013
    Assignees: Powerchip Corporation, Powerchip Technology Corporation
    Inventors: Takashi Miida, Riichiro Shirota, Hideki Arakawa, Ching Sung Yang, Tzung Ling Lin