Abstract: A voltage-stacked system includes a first voltage source, at least one second voltage source, a master monitoring circuit and at least one slave monitoring circuit. The first voltage source and the at least one second voltage source are coupled in series. The master monitoring circuit is coupled to the first voltage source, and arranged for monitoring and controlling the first voltage source and transmitting a monitoring signal. The at least one slave monitoring circuit is respectively coupled to the at least one second voltage source and the master monitoring circuit for monitoring and controlling the at least one second voltage source, and accordingly sending a response signal to the master monitoring circuit.
Type:
Grant
Filed:
October 18, 2013
Date of Patent:
July 12, 2016
Assignee:
POWERFLASH TECHNOLOGY CORPORATION
Inventors:
Chun-Ming Chen, Chang-Fu Hsia, Sheng-An Yang, Yuan-Chi Ho
Abstract: A voltage-stacked system includes a first voltage source, at least one second voltage source, a master monitoring circuit and at least one slave monitoring circuit. The first voltage source and the at least one second voltage source are coupled in series. The master monitoring circuit is coupled to the first voltage source, and arranged for monitoring and controlling the first voltage source and transmitting a monitoring signal. The at least one slave monitoring circuit is respectively coupled to the at least one second voltage source and the master monitoring circuit for monitoring and controlling the at least one second voltage source, and accordingly sending a response signal to the master monitoring circuit.
Type:
Application
Filed:
October 18, 2013
Publication date:
December 18, 2014
Applicant:
POWERFLASH TECHNOLOGY CORPORATION
Inventors:
Chun-Ming Chen, Chang-Fu Hsia, Sheng-An Yang, Yuan-Chi Ho
Abstract: In a smart battery device, a battery pack having a plurality of battery cells is provided. During charging, if the voltage of each battery cell does not exceed the maximum operational voltage associated with individual battery cell, the battery pack is charged by a first voltage. If the voltage of any battery cell is not smaller than the maximum operational voltage associated with individual battery cell, the battery pack is charged by a second voltage smaller than the first voltage.
Abstract: A memory structure includes a first memory cell and a second memory cell located at an identical bit line and adjacent to the first memory cell. Each memory cell includes a substrate, a source, a drain, a charge storage device, and a gate. A method for programming the memory structure includes respectively providing a first gate biasing voltage and a second gate biasing voltage to the gates of the first memory cell and the second memory cell, boosting an absolute value of a channel voltage of the first memory cell to generate electron and hole pairs at the drain of the second memory cell through gate-induced drain leakage or band-to-band tunneling, and injecting the hole of the generated electron and hole pairs into the charge storage device of the first memory cell to program the first memory cell.
Type:
Grant
Filed:
November 11, 2010
Date of Patent:
May 31, 2011
Assignee:
Powerflash Technology Corporation
Inventors:
Riichiro Shirota, Ching-Hsiang Hsu, Cheng-Jye Liu
Abstract: The present invention provides a mobile phone accessing system. The mobile phone accessing system comprises: a mobile phone having a first International Mobile Equipment Identity (IMEI) code; and a storage device comprising a first storage region for storing data, a second storage region for storing a second IMEI code, and a controller coupled to the first storage region and the second storage region for executing a security check function to determine whether the mobile phone is qualified to access the first storage region according to the first IMEI code.
Type:
Grant
Filed:
December 23, 2008
Date of Patent:
May 3, 2011
Assignee:
Powerflash Technology Corporation
Inventors:
Tung-Cheng Kuo, Ching-Sung Yang, Ruei-Ling Lin, Cheng-Jye Liu
Abstract: A memory structure includes a first memory cell and a second memory cell located at an identical bit line and adjacent to the first memory cell. Each memory cell includes a substrate, a source, a drain, a charge storage device, and a gate. A method for programming the memory structure includes respectively providing a first gate biasing voltage and a second gate biasing voltage to the first memory cell and the second memory cell, boosting the absolute value of a channel voltage of the first memory cell to generate electron and hole pairs at the drain of the second memory cell through gate-induced drain leakage or band-to-band tunneling, and injecting the electron of the generated electron and hole pairs into the charge storage device of the first memory cell to program the first memory cell.
Type:
Grant
Filed:
June 24, 2008
Date of Patent:
December 21, 2010
Assignee:
Powerflash Technology Corporation
Inventors:
Riichiro Shirota, Ching-Hsiang Hsu, Cheng-Jye Liu