Abstract: An off-axis light source is described, including an X-dipole illumination pattern, a Y-dipole illumination pattern and a quadrupole illumination pattern at the illumination surface thereof, wherein the illumination area of the quadrupole illumination pattern is smaller than that of the X- or Y-dipole illumination pattern. A light screen plate is also described, having corresponding openings therein and can be used to form the above off-axis light source. A method of defining different types of patterns with a single exposure is also described, which utilizes the above off-axis light source.

Abstract: A non-volatile memory device having a substrate, an n type well, a p type well, a control gate, a composite dielectric layer, a source region and a drain region is provided. A trench is formed in the substrate. The n type well is formed in the substrate. The p type well is formed in the substrate above the n type well. The junction of p type well and the n type well is higher than the bottom of the trench. The control gate which protruding the surface of substrate is formed on the sidewalls of the trench. The composite dielectric layer is formed between the control gate and the substrate. The composite dielectric layer includes a charge-trapping layer. The source region and the drain region are formed in the substrate of the bottom of the trench respectively next to the sides of the control gate.

Abstract: A flash memory cell structure has a substrate, a select gate, a first-type doped region, a shallow second-type doped region, a deep second-type doped region, and a doped source region. The substrate has a stacked gate. The select gate is formed on the substrate and adjacent to the stacked gate. The first-type ion formed region is doped in the substrate and adjacent to the select gate as a drain. The shallow second-type doped region is formed on one side of the first-type doped region below the stacked gate. The deep second-type doped region, which serves as a well, is formed underneath the first-type doped region with one side bordering on the shallow second-type doped region. The doped source region is formed on a side of the shallow second-type doped region as a source.

Abstract: A flash memory cell array comprises a substrate, a string of memory cell structures and source region/drain region. Each of memory cell structures includes a stack gate structure including a select gate dielectric layer, a select gate and a gate cap layer formed on the substrate; a spacer is set on the sidewall of the select gate; a control gate connected to the stack gate structure is set on the one side of the stack gate structure; a floating gate is set between the control gate and the substrate; an inter-gate dielectric layer is set between the control gate and the floating gate; and a tunneling dielectric layer is set between the floating gate and the substrate. The source region/drain region is set in the substrate near outer control gate and stack gate structure of the flash memory cell array.

Abstract: A sputtering apparatus is provided. The sputtering apparatus comprises cooling water system having a temperature-controlling device for controlling the temperature of the sidewalls of the reaction chamber. During the deposition process of titanium/titanium nitride, the sidewall temperature of the chamber is controlled at about 50° C.˜70° C. for reducing the difference of temperature distribution in the chamber so that the reaction temperature within the reaction chamber can be rendered substantially uniform.

Abstract: A probe card for use in a multi-chip probing test equipment with reduced noise coupling effect is disclosed. It contains (a) a multi-layer circuit board with a window formed at a central portion thereof, the multi-layer circuit board containing a number of contact points arranged on the surface ofthe multi-layer circuit board for electrically contacting the test head of the test equipment; (b) a plurality of downward pointing testing pins attached to the multi-layer circuit board and electrically connected to the contact points on the surface ofthe multi-layer circuit board, the testing pins being arranged to face a plurality of semiconductor chips so as to tests to be conducted on the plurality of semiconductor chips; (c) a ground layer formed in the multi-layer circuit board; and (d) a plurality of spaced apart ground paths arranged across the window of the multi-layer circuit board.