Abstract: The present application is directed at pin programming od controllers for power converters and provides for the programming of a plurality of different controller parameters using a single programming resistor. The value of the programming resistor is used as a pointer to select a table storing a plurality of different settings for the controller.

Abstract: The present application relates to controllers using current mode control to control the operation of switching power supplies such as DC-DC converters. The application provides an inductor current.

Abstract: The present application relates to power converters, particularly switch mode power converters sharing a load in which the converters are operated to share stresses between them. The application provides a controller (108) in which a stress share control loop (108a, 108b) is provided to ensure the associated converter is operating at an average stress. The stress share control loop has a proportional and an integral term in its feedback path. The integral term may be enabled or disabled. In use, the integral term is enabled in all but one controller.

Abstract: The present application is directed at pin programming od controllers for power converters and provides for the programming of a plurality of different controller parameters using a single programming resistor. The value of the programming resistor is used as a pointer to select a table storing a plurality of different settings for the controller.

Abstract: Methods and circuits for power supply arrangement and control are disclosed herein. More specifically the application relates to a control method and a controller for a DC-to-DC converter, such as a synchronous Buck converter, which implements a transient detection scheme together with response generation to allow the converter to recover from a positive and/or negative load current step in the robust way, with low undershoot/overshoot at the output voltage. The control method may be implemented by either an analog or a digital circuit. The controller may be integrated with existing controller schemes (such as voltage-mode controllers) to provide superior dynamic performance during large-signal transient conditions while providing stable operation during steady state conditions. The methods and circuits provided herein are applicable to Buck converters and Buck-derived converters such as forward, push-pull, half-bridge, and full-bridge converters.

Abstract: The present application provides a tunable compensator providing a control signal to control a switch in a power supply. A measurement is taken of the level of activity of the control signal. This measurement is used to introduce a bias into a tuner tuning the compensator when the amount of activity in the control signal drops.

Abstract: The present application provides a method of calculating DC-DC converter power losses without the requirement for a measurement of input current. The application also describes the use of such a calculation to determine the optimum point for switchover between a single phase mode or dual phase mode in a two phase DC-DC power supply.

Abstract: Methods and circuits for power supply arrangement and control are disclosed herein. More specifically the application relates to a control method and a controller for a DC-to-DC converter, such as a synchronous Buck converter, which implements a transient detection scheme together with response generation to allow the converter to recover from a positive and/or negative load current step in the robust way, with low undershoot/overshoot at the output voltage. The control method may be implemented by either an analog or a digital circuit. The controller may be integrated with existing controller schemes (such as voltage-mode controllers) to provide superior dynamic performance during large-signal transient conditions while providing stable operation during steady state conditions. The methods and circuits provided herein are applicable to Buck converters and Buck-derived converters such as forward, push-pull, half-bridge, and full-bridge converters.

Abstract: The present application is directed at methods of controlling power supplies. In particular the present application employs an analog compensator to control the power stage of the power supply with a digital tuner employed to adaptively tune the operation of the analog compensator.

Abstract: The present disclosure is directed generally to switch mode power supplies operating in a master-slave configuration and provides a method of synchronizing the PWM outputs from the master and slave devices to avoid problems such, for example, as the generation of beat frequencies.

Abstract: The Application is directed at arrangements at which switch mode power converters share a common load. More particularly, the application provides a masterless arrangement in which no single converter controls the operation of the other converters. This is achieved by an arrangement in which each converter attempts to share its current measurement with other converters through an arbitration scheme employed on a data line, with the winning converter providing a defacto current measurement; for example, a maximum or minimum, to the overall arrangement.

Abstract: The present application provides an adaptive control system for controlling a plant in particular a DC-DC power converter. The control system has two controllers of differing characteristics. The output of the individual controllers H0 and H1 are combined together to provide a combined control signal H to the plant, where H=?H1+(1??)H0 and where the adaptive control system is tuned by adjusting the value of ? between 0 and 1 to find an optimum control position.

Abstract: The present application is directed at methods of controlling power supplies. In particular the present application employs an analog compensator to control the power stage of the power supply with a digital tuner employed to adaptively tune the operation of the analog compensator.

Abstract: A DPWM (1) has a locked loop (4) which receives an input clock signal and provides an out-of-phase delayed clock at the output of each cell in the loop (35). A multiplexer (5) selects one of the cell outputs at any one time. This allows the DPWM (1) to have a greater resolution which would otherwise be achieved with the same input clock. The resolution is further increased using an interpolator. A programmable module (2) has a control block (20) which interfaces with external CPU and DSP hosts and transmits programmed parameters to finite state machine controllers (15), each providing an independent output.

Abstract: The present invention relates to power converters of the type known generally as switch mode power converters (SMPCs). In particular, the present invention addresses the problem of reducing thermal stress across the phases of a multi phase converter. Specifically, a method of controlling a multi-phase switch mode power arrangement is provided. The multi-phase arrangement comprises a plurality of phases configured to deliver DC power to a common load. The method comprises the steps of: determining the thermal stress of each phase along with at least one other stress for each phase and controlling the share of DC power provided by the individual phases in an effort to equalize the thermal and other stress across the individual phases.

Abstract: The present disclosure is directed generally to switch mode power supplies operating in a master-slave configuration and provides a method of synchronizing the PWM outputs from the master and slave devices to avoid problems such, for example, as the generation of beat frequencies.

Abstract: A DPWM (1) has a delay lock loop (4) which receives an input clock signal and provides an out-of-phase delayed clock at the output of each of eight delay cells (35). A multiplexer (5) selects one of the delay cell outputs at any one time. This allows the DPWM (1) to have eight times the resolution which would otherwise be achieved with the same input clock. A programmable module (2) has a control block (20) which interfaces with external CPU and DSP hosts and transmits programmed parameters to finite state machine controllers (15), each providing an independent output.

Abstract: A DPWM (1) has a delay lock loop (4) which receives an input clock signal and provides an out-of-phase delayed clock at the output of each of eight delay cells (35). A multiplexer (5) selects one of the delay cell outputs at any one time. This allows the DPWM (1) to have eight times the resolution which would otherwise be achieved with the same input clock. A programmable module (2) has a control block (20) which interfaces with external CPU and DSP hosts and transmits programmed parameters to finite state machine controllers (15), each providing an independent output.