Abstract: A computer processing system having an isogeny-based cryptosystem for randomizing computational hierarchy to protect against side-channel analysis in isogeny-based cryptosystems.

Abstract: A low footprint hardware architecture for a Dilithium digital signature scheme that includes a plurality of submodules resident in a coprocessor that are operably configured to carry out a plurality of mathematical instructions employed in performing a plurality of cryptographic Dilithium algorithms at security levels 2, 3, and 5 of a final version of a NIST submission package.

Abstract: An area efficient architecture for lattice based key encapsulation and digital signature generation having a co-processor with a polynomial arithmetic submodule configured to process polynomial arithmetic and generate integer values representing polynomial coefficients, a hash submodule operably configured to perform hash operations and to generate pseudorandom numbers, a polynomial format submodule communicatively coupled to the polynomial arithmetic submodule and the hash submodule and operably configured to encode polynomials and decode polynomials, a memory bank communicatively coupled with and operably configured to receive and store temporary values from the polynomial arithmetic submodule, the hash submodule, the polynomial format submodule, and a data interface, and with a control unit operably configured to manage the data interface at selectively controlled time intervals and to utilize the polynomial arithmetic submodule, the hash submodule, and the polynomial format submodule to perform the plural

Abstract: An area efficient architecture for lattice based key encapsulation and digital signature generation having a co-processor with a polynomial arithmetic submodule configured to process polynomial arithmetic and generate integer values representing polynomial coefficients, a hash submodule operably configured to perform hash operations and to generate pseudorandom numbers, a polynomial format submodule communicatively coupled to the polynomial arithmetic submodule and the hash submodule and operably configured to encode polynomials and decode polynomials, a memory bank communicatively coupled with and operably configured to receive and store temporary values from the polynomial arithmetic submodule, the hash submodule, the polynomial format submodule, and a data interface, and with a control unit operably configured to manage the data interface at selectively controlled time intervals and to utilize the polynomial arithmetic submodule, the hash submodule, and the polynomial format submodule to perform the plural

Abstract: A computer processing hardware architecture system for the Kyber lattice-based cryptosystem which is created with high resource reuse in the compression and decompression module, the operation unit, the binomial samplers, and the operation ordering, wherein the architecture system includes an internal controller operably configured to independently accelerate a plurality of cryptographic Kyber algorithms at all NIST-recommended post-quantum cryptography security levels and is operably coupled to a singular module operably configured to perform compression and decompression as specified in Kyber, perform arithmetic operations utilized in the plurality of cryptographic Kyber algorithms, and reuse hardware resources for all the arithmetic operations utilized in the plurality of cryptographic Kyber algorithms.

Abstract: A computer processing system have includes a processing unit operably configured to perform a plurality of exponentiation operations and a cryptosystem controller operably configured to load an exponent from the at least one exponentiation operation from a memory to an algorithm controller by first applying a function, wherein the algorithm controller including at least one set of shift registers operably configured to shift a plurality of digits and operably configured to utilize at least one of the plurality of digits as an output.

Abstract: At least one computer processor configured with a single prime field accelerator having software-based instructions operably configured to compute both isogeny-based cryptography equations and elliptic curve cryptography equations using a plurality of shared computations resident on a shared memory storage and that include finite field arithmetic and elliptic curve group arithmetic sequentially computed with an architecture controller.

Abstract: A low footprint resource sharing hardware architecture that is implemented as a co-processor and is operably configured to perform a plurality of cryptographic algorithms for Dilithium-DSA at all NIST-recommended post-quantum cryptography security levels and a plurality of cryptographic algorithms for Kyber-KEM at all NIST-recommended post-quantum cryptography security levels. The architecture also includes a singular arithmetic unit 104 operably configured perform all arithmetic operations required in the plurality of cryptographic algorithms for Kyber-KEM and the plurality of cryptographic algorithms for Dilithium-DSA and a singular sampling unit operably configured to sample all vectors and matrices required in the plurality of cryptographic algorithms for Kyber-KEM and the plurality of cryptographic algorithms for Dilithium-DSA.

Abstract: A computer processing hardware architecture system for the Kyber lattice-based cryptosystem which is created with high resource reuse in the compression and decompression module, the operation unit, the binomial samplers, and the operation ordering.

Abstract: A computer-implemented method and system for computing large-degree isogenies of a base degree raised to a power of form ak+b and including the steps of providing at least one computer processor resident on an electronic computing device, performing, with the at least one processor, a large-degree isogeny by chaining together a plurality of scalar point multiplications, a plurality of isogeny computations, and a plurality of isogeny evaluations, wherein the large-degree isogeny includes a sequence storing at least one pivot point computed by one of the plurality of scalar point multiplications followed by an isogeny computation of degree b, performing at least one of the plurality of isogeny evaluations following one of the plurality isogeny computations, and performing an ak-isogeny through another sequence of a isogeny computations.

Abstract: A computer processing system for validating isogeny-based cryptography keys having an electronic computing device with an isogeny-based cryptosystem operably configured to validate public keying material including an elliptic curve by simultaneously computing an elliptic curve supersingularity check along with an elliptic curve public point check.

Abstract: A computer processing system for validating isogeny-based cryptography keys having an electronic computing device with an isogeny-based cryptosystem operably configured to validate public keying material including an elliptic curve by simultaneously computing an elliptic curve supersingularity check along with an elliptic curve public point check.

Abstract: At least one computer processor configured with a single prime field accelerator having software-based instructions operably configured to compute both isogeny-based cryptography equations and elliptic curve cryptography equations using a plurality of shared computations resident on a shared memory storage and that include finite field arithmetic and elliptic curve group arithmetic sequentially computed with an architecture controller.

Abstract: A computer processing system having an isogeny-based cryptosystem for randomizing computational hierarchy to protect against side-channel analysis in isogeny-based cryptosystems.

Abstract: A computer processing system having at least one accelerator operably configured to compute modular multiplication with a modulus of special form and having a systolic carry-save architecture configured to implement Montgomery multiplication and reduction and having multiple processing element types composed of Full Adders and AND gates.

Abstract: A computer processing system for reducing a processing footprint in cryptosystems utilizing quadratic extension field arithmetic such as pairing-based cryptography, elliptic curve cryptography, code-based cryptography and post-quantum elliptic curve cryptography that includes at least one computer processor having a register file with three processor registers operably configured to implement quadratic extension field arithmetic equations in a finite field of Fp2 and a multiplexer operably configured to selectively shift from each of the three processor registers in sequential order to generate modular additional results and modular multiplication results from the three processor registers.

Abstract: A computer processing system for reducing a processing footprint in cryptosystems utilizing quadratic extension field arithmetic such as pairing-based cryptography, elliptic curve cryptography, code-based cryptography and post-quantum elliptic curve cryptography that includes at least one computer processor having a register file with three processor registers operably configured to implement quadratic extension field arithmetic equations in a finite field of Fp2 and a multiplexer operably configured to selectively shift from each of the three processor registers in sequential order to generate modular additional results and modular multiplication results from the three processor registers.

Abstract: A computer processing hardware architecture system in a highly secure isogeny based cryptosystem that includes at least one computer processor operably configured to target accelerating operations involved in isogenies on elliptic curves and having a secret key register operably configured to register a secret key, a pseudo-random function, and a secret message buffer, each operably written to by a 2:4 demultiplexer circuit operably configured to receive outside data in regions therein and read by a 4:2 multiplexer circuit.

Abstract: A computer processing system and method for reducing memory footprint that includes initiating, through at least one computer processor, a cryptography session utilizing an i-degree isogeny arithmetic computation having chained computations therein. The cryptography session includes implementing a first iteration cycle, of a plurality of iteration cycles, and a implementing a remaining amount of the plurality of iteration cycles, each of the plurality iteration cycles computing isogenies using a compressed Z value to complete the -degree isogeny arithmetic computation. The first iteration cycle includes individually computing a plurality of sequentially occurring pivot points within the chained computations, implementing a Co—Z algorithm within the plurality of sequentially occurring pivot points to compute and store the compressed Z value on one of the plurality of temporary registers and computing a first isogeny of the -degree isogeny arithmetic computations using the compressed Z value.

Abstract: A computer processing system and method for reducing memory footprint that includes initiating, through at least one computer processor, a cryptography session utilizing an -degree isogeny arithmetic computation having chained computations therein. The cryptography session includes implementing a first iteration cycle, of a plurality of iteration cycles, and a implementing a remaining amount of the plurality of iteration cycles, each of the plurality iteration cycles computing isogenies using a compressed Z value to complete the -degree isogeny arithmetic computation. The first iteration cycle includes individually computing a plurality of sequentially occurring pivot points within the chained computations, implementing a Co-Z algorithm within the plurality of sequentially occurring pivot points to compute and store the compressed Z value on one of the plurality of temporary registers and computing a first isogeny of the -degree isogeny arithmetic computations using the compressed Z value.