Abstract: A computer processing system and method for computing large-degree isogenies having a computer processor resident on an electronic computing device operably configured to execute computer-readable instructions programmed to perform a large-degree isogeny operation by chaining together a plurality of scalar point multiplications, a plurality of isogeny computations, and a plurality of isogeny evaluations.

Abstract: A computer processing system that includes at least one arithmetic logic unit in a computer processing device and includes at least one addition circuit operably configured to compute addition operations, operably configured to receive two numerical inputs, and operably configured to compute a sum and includes at least one modular multiplication circuit operably configured to receive the sum from the at least one addition circuit, receive at least one other numerical input, and receive a numerical modulus to perform a modular multiplication operation and generate a modular multiplication operation result.

Abstract: A hardware architecture configured to implement ASCON cryptographic algorithms and protect against side-channel attacks that includes a co-processor having a controller, a logic gate operably configured to receive a data input and ASCON state memory data in an initial cycle of permutation iterations, a multiplexor operably configured to direct data input from the logic gate based on a signal received from the controller and in the initial cycle of permutation iterations, an ASCON state memory operably configured to receive the processed data in the initial cycle of permutation iterations, and that is operably configured to implement a permutation round configured to receive the data input directly from the logic gate through the multiplexor and process the data input utilizing a permutation function to generate processed data and in the initial cycle of permutation iterations.

Abstract: This invention presents a computer processing system and method designed to execute cryptographic operations while providing selective protection against side-channel attacks. It comprises a configuration of unprotected and protected hardware modules, the latter of which is equipped with data isolators, and a protected arithmetic logic unit (ALU) for secure data processing. The system enhances cryptographic security by selectively transmitting and computing input shares to generate side-channel protected output shares, ensuring robust protection during cryptographic operations.

Abstract: A computer-implemented method for computing an unbalanced L-tree for hash-based signatures used in post-quantum cryptographic authentication that includes providing a computer with at least one processor operably configured to carry out a post-quantum cryptographic authentication session and having computer-readable instructions to generate a root of an unbalanced L-tree in the post-quantum cryptographic authentication session, computing a maximum 2n number of leaf node pairs formed on the unbalanced L-tree and hashing each pair of adjacent leaf nodes forming the maximum 2n number of leaf node pairs with a stacked-based root implementation until reaching an unpaired stacked node output, and subjecting remaining leaf nodes formed on the unbalanced L-tree with an L-tree-based root implementation and computing the remaining leaf nodes with the unpaired stacked node output to generate the root of the unbalanced L-tree formed as part of the post-quantum cryptographic authentication session.

Abstract: A computer processing system configured to perform lattice-based cryptographic primitives with resistance to side-channel attacks with a computer processing architecture operably configured to perform at least one of key generation, key encapsulation, and key decapsulation and process security sensitive data, a sampling submodule performing hashing operations and centered binomial sampling routines, a polynomial arithmetic unit performing polynomial multiplication, polynomial addition, and polynomial subtraction by processing the security sensitive data that is divided into shares stored on a plurality of memory banks, an auxiliary submodule mathematical operations, a data interface unit operably configured to perform input and output operations and to input data and output data in shares, and de-serialize the input data into polynomial coefficients utilized by the polynomial arithmetic unit, and a controller submodule operably configured to sequence any operations needed to perform the at least one of key ge

Abstract: A computer processing system configured to effectuate lower-order masking in a higher-order masked design that includes a DOM Multiplication gate of order M operably configured to receive M+1 data shares for each of a plurality of variables and operably configured to perform a lower order masking of N. As used herein, M is greater than N, by disabling at least one cross-domain computation of the M+1 data shares between N+1 data shares and M?N data shares. To that end, the system and method of effectuating lower-ordered masking in a higher-order masked design beneficially by being operable to disable cross-domain computations to perform the lower-order masked operations.

Abstract: A computer processing system that includes at least one arithmetic logic unit in a computer processing device and includes at least one addition circuit operably configured to compute addition operations, operably configured to receive two numerical inputs, and operably configured to compute a sum and includes at least one modular multiplication circuit operably configured to receive the sum from the at least one addition circuit, receive at least one other numerical input, and receive a numerical modulus to perform a modular multiplication operation and generate a modular multiplication operation result

Abstract: A computer processing system have includes a processing unit operably configured to perform a plurality of exponentiation operations and a cryptosystem controller operably configured to load an exponent from the at least one exponentiation operation from a memory to an algorithm controller by first applying a function, wherein the algorithm controller including at least one set of shift registers operably configured to shift a plurality of digits and operably configured to utilize at least one of the plurality of digits as an output.

Abstract: A computer processing system that includes an elliptic curve computational unit in a computer processing device operably configured to perform an elliptic curve arithmetic operation with a sequence of field operations, receive an elliptic curve numerical input that includes at least one elliptic curve coefficient of an elliptic curve that is operably utilized in the elliptic curve arithmetic operation, receive an elliptic curve coefficient randomization numerical input that is operably configured for use in the elliptic curve arithmetic operation, compute a new and substantially equivalent elliptic curve representation for the elliptic curve coefficient of the elliptic curve by performing a field operation with the elliptic curve numerical input and the elliptic curve coefficient randomization numerical input, and utilize the new and substantially equivalent elliptic curve representation in the sequence of field operations, and having an arithmetic output port operably configured to output a numerical resu

Abstract: A computer processing system and method for computing large-degree isogenies having a computer processor resident on an electronic computing device operably configured to execute computer-readable instructions programmed to perform a large-degree isogeny operation by chaining together a plurality of scalar point multiplications, a plurality of isogeny computations, and a plurality of isogeny evaluations.

Abstract: A computer processing isogeny-based cryptosystem method and architecture having at least one cryptosystem controller operably configured to initiate and supervise isogeny-based cryptosystem operations, at least one read-only memory operably configured to read instruction sequences and constants used to perform operations within an isogeny-based cryptosystem, at least one random-access memory operably configured to read and write intermediate data for the isogeny-based cryptosystem, and at least one of an isogeny computational unit operably configured to perform isogeny-based arithmetic. The isogeny computational unit also includes a program control unit operably configured to control the operations within the isogeny-based cryptosystem through a sequence of instructions and an instruction control unit operably configured to control an arithmetic logic unit and random-access memory interactions that include loading and storing data to the least one random-access memory.

Abstract: A computer processing system having an isogeny-based cryptosystem for randomizing computational hierarchy to protect against side-channel analysis in isogeny-based cryptosystems.

Abstract: A low footprint hardware architecture for a Dilithium digital signature scheme that includes a plurality of submodules resident in a coprocessor that are operably configured to carry out a plurality of mathematical instructions employed in performing a plurality of cryptographic Dilithium algorithms at security levels 2, 3, and 5 of a final version of a NIST submission package.

Abstract: An area efficient architecture for lattice based key encapsulation and digital signature generation having a co-processor with a polynomial arithmetic submodule configured to process polynomial arithmetic and generate integer values representing polynomial coefficients, a hash submodule operably configured to perform hash operations and to generate pseudorandom numbers, a polynomial format submodule communicatively coupled to the polynomial arithmetic submodule and the hash submodule and operably configured to encode polynomials and decode polynomials, a memory bank communicatively coupled with and operably configured to receive and store temporary values from the polynomial arithmetic submodule, the hash submodule, the polynomial format submodule, and a data interface, and with a control unit operably configured to manage the data interface at selectively controlled time intervals and to utilize the polynomial arithmetic submodule, the hash submodule, and the polynomial format submodule to perform the plural

Abstract: An area efficient architecture for lattice based key encapsulation and digital signature generation having a co-processor with a polynomial arithmetic submodule configured to process polynomial arithmetic and generate integer values representing polynomial coefficients, a hash submodule operably configured to perform hash operations and to generate pseudorandom numbers, a polynomial format submodule communicatively coupled to the polynomial arithmetic submodule and the hash submodule and operably configured to encode polynomials and decode polynomials, a memory bank communicatively coupled with and operably configured to receive and store temporary values from the polynomial arithmetic submodule, the hash submodule, the polynomial format submodule, and a data interface, and with a control unit operably configured to manage the data interface at selectively controlled time intervals and to utilize the polynomial arithmetic submodule, the hash submodule, and the polynomial format submodule to perform the plural

Abstract: A computer processing hardware architecture system for the Kyber lattice-based cryptosystem which is created with high resource reuse in the compression and decompression module, the operation unit, the binomial samplers, and the operation ordering, wherein the architecture system includes an internal controller operably configured to independently accelerate a plurality of cryptographic Kyber algorithms at all NIST-recommended post-quantum cryptography security levels and is operably coupled to a singular module operably configured to perform compression and decompression as specified in Kyber, perform arithmetic operations utilized in the plurality of cryptographic Kyber algorithms, and reuse hardware resources for all the arithmetic operations utilized in the plurality of cryptographic Kyber algorithms.

Abstract: A computer processing system have includes a processing unit operably configured to perform a plurality of exponentiation operations and a cryptosystem controller operably configured to load an exponent from the at least one exponentiation operation from a memory to an algorithm controller by first applying a function, wherein the algorithm controller including at least one set of shift registers operably configured to shift a plurality of digits and operably configured to utilize at least one of the plurality of digits as an output.

Abstract: At least one computer processor configured with a single prime field accelerator having software-based instructions operably configured to compute both isogeny-based cryptography equations and elliptic curve cryptography equations using a plurality of shared computations resident on a shared memory storage and that include finite field arithmetic and elliptic curve group arithmetic sequentially computed with an architecture controller.

Abstract: A low footprint resource sharing hardware architecture that is implemented as a co-processor and is operably configured to perform a plurality of cryptographic algorithms for Dilithium-DSA at all NIST-recommended post-quantum cryptography security levels and a plurality of cryptographic algorithms for Kyber-KEM at all NIST-recommended post-quantum cryptography security levels. The architecture also includes a singular arithmetic unit 104 operably configured perform all arithmetic operations required in the plurality of cryptographic algorithms for Kyber-KEM and the plurality of cryptographic algorithms for Dilithium-DSA and a singular sampling unit operably configured to sample all vectors and matrices required in the plurality of cryptographic algorithms for Kyber-KEM and the plurality of cryptographic algorithms for Dilithium-DSA.