Patents Assigned to Praesagus, Inc.
  • Patent number: 7243316
    Abstract: A mask design is generated for patterning a test wafer using a lithographic or etch process, the process is characterized based on the patterned test wafer, and a pattern-dependent model is used based on the characterization to predict characteristics of integrated circuits that are to be fabricated by the lithographic or etch process.
    Type: Grant
    Filed: December 17, 2002
    Date of Patent: July 10, 2007
    Assignee: Praesagus, Inc.
    Inventors: David White, Taber H. Smith
  • Publication number: 20070101305
    Abstract: A method and system are described to reduce process variation as a result of the electrochemical deposition (ECD), also referred to as electrochemical plating (ECP), and chemical mechanical polishing (CMP) processing of films in integrated circuit manufacturing processes. The described methods use process variation and electrical impact to direct the insertion of dummy fill into an integrated circuit.
    Type: Application
    Filed: December 19, 2006
    Publication date: May 3, 2007
    Applicant: Praesagus, Inc.
    Inventors: Taber Smith, Vikas Mehrotra, David White
  • Patent number: 7174520
    Abstract: Variations are characterized in feature dimensions of an integrated circuit that is to be fabricated in accordance with a design by a process that produces topographical variation in the integrated circuit, the variations in feature dimension being caused by the topographical variations. The process includes lithography or etch. Predicted characteristics are verified to conform to the design, the characteristics including feature dimensions or electrical characteristics. A process is selected for use in fabricating the integrated circuit based on the relative predicted variations. Chip-level features of a design of an integrated circuit are verified for manufacture within focus limitations of a lithographic tool. Whether a design of a level of an integrated circuit can be lithographically imaged in accordance with the design is predicted, and if it cannot be, the design or processing parameters are adjusted so that it can be.
    Type: Grant
    Filed: December 17, 2002
    Date of Patent: February 6, 2007
    Assignee: Praesagus, Inc.
    Inventors: David White, Taber H. Smith
  • Patent number: 7152215
    Abstract: A method and system are described to reduce process variation as a result of the electrochemical deposition (ECD), also referred to as electrochemical plating (ECP), and chemical mechanical polishing (CMP) processing of films in integrated circuit manufacturing processes. The described methods use process variation and electrical impact to direct the insertion of dummy fill into an integrated circuit.
    Type: Grant
    Filed: June 7, 2002
    Date of Patent: December 19, 2006
    Assignee: Praesagus, Inc.
    Inventors: Taber H. Smith, Vikas Mehrotra, David White
  • Patent number: 7124386
    Abstract: A method and system are described to reduce process variation as a result of the electrochemical deposition (ECD), also referred to as electrochemical plating (ECP), and chemical mechanical polishing (CMP) processing of films in integrated circuit manufacturing processes. The described methods use process variation and electrical impact to direct the insertion of dummy fill into an integrated circuit.
    Type: Grant
    Filed: June 7, 2002
    Date of Patent: October 17, 2006
    Assignee: Praesagus, Inc.
    Inventors: Taber H. Smith, Vikas Mehrotra, David White
  • Patent number: 7062730
    Abstract: A mask design is generated for patterning a test wafer using a lithographic or etch process, the process is characterized based on the patterned test wafer, and a pattern-dependent model is used based on the characterization to predict characteristics of integrated circuits that are to be fabricated by the lithographic or etch process.
    Type: Grant
    Filed: December 17, 2002
    Date of Patent: June 13, 2006
    Assignee: Praesagus, Inc.
    Inventors: David White, Taber H. Smith
  • Patent number: 7039895
    Abstract: A pattern-dependent model is used to predict characteristics of an integrated circuit that is to be fabricated in accordance with a design by a process. The process includes (a) a fabrication process that will impart topographical variation to the integrated circuit and (b) a lithography or etch process, the lithography or etch process using a mask produced from the design. The lithography or etch process and the fabrication process interact to cause the predicted characteristics to differ from the design. The mask is adjusted in response to characteristics predicted by the model, to reduce the effect of the interacting of the lithography or etch process and the fabrication process.
    Type: Grant
    Filed: December 17, 2002
    Date of Patent: May 2, 2006
    Assignee: Praesagus, Inc.
    Inventors: David White, Taber H. Smith