Abstract: One embodiment of the present invention includes a control circuit, an increment register, and an accumulator. The control circuit generates a channel enable signal based on control information from a processor at a first clock signal having a first clock frequency. The channel enable signal selects a channel for a satellite in a global positioning system (GPS). The channel operates at a coarse/acquisition (C/A) clock signal having a second clock frequency. The increment register stores an increment value for the selected channel at the first clock signal. The accumulator generates a pseudo-random noise (PN) clock signal to a PN generator using the increment value.

Abstract: One embodiment of the present invention includes a first memory, an address counter, and an adder. The first memory having KN locations stores K sums of mixer samples during an epoch interval. The mixer samples are generated at a first clock frequency from a mixer for N channels corresponding to N satellites in a global positioning system (GPS) receiver. The address counter generates an address modulo-KN corresponding to a first location in the memory at the first clock frequency. The adder adds one of the mixer samples to contents of the first location to generate a sum. The sum is written into the first location.

Abstract: One embodiment of the present invention includes a circular shift register, K storage elements, and a code register. The circular shift register having N data samples circularly shifts a first data sample of the N data samples into a data position at a first clock frequency. The N data samples correspond to signal received from one of K satellites in a global positioning system (GPS). The N data samples are loaded into the circular shift register at a second clock frequency. The K storage elements store K code sequences, respectively. Each of the K code sequences has N code samples and includes a first code sample being written at a code position corresponding to the data position at a third clock frequency. The K storage elements correspond to the K satellites. The code register stores the N code samples loaded from one of the K storage elements at a fourth clock frequency. The fourth clock frequency is K times faster than the first clock frequency.

Abstract: One embodiment of the present invention includes a gating circuit, a demultiplexer, and an integrator. The gating circuit gates an input sample with a first clock, the input sample being clocked by a sampling clock N times faster than the first clock. The demultiplexer demultiplexes the gated input sample to generate in-phase and quadrature samples. The integrator integrates the in-phase and quadrature samples to generate in-phase and quadrature decimated samples corresponding to the in-phase and quadrature samples, respectively. Each of the in-phase and quadrature decimated samples having K bits.