Patents Assigned to Primarian, Inc.
  • Phase lock loop destress circuit
    Patent number: 6642799
    Abstract: An improved phase lock loop destress circuit is described. The PLL circuit includes a loop destress logic circuit and a coarse tune digital-to-analog converter, which are coupled to a summer and driver, which in turn is coupled to a voltage controlled oscillator. The loop destress logic circuit is configured to automatically select a digital word for use in coarse tuning the voltage controlled oscillator.
    Type: Grant
    Filed: November 1, 2001
    Date of Patent: November 4, 2003
    Assignee: Primarian, Inc.
    Inventor: Benjamim Tang