Abstract: A semiconductor device includes a first processor configured to generate a first memory physical address and a first memory request; a second processor configured to generate a second memory physical address and a second memory request; a first system-on-chip physically connected to the first processor and configured to convert the first memory physical address into a first device address; a second system-on-chip physically connected to the second processor and the first system-on-chip and configured to convert the second memory physical address into a second device address; and a first memory and a second memory respectively and physically connected to the first system-on-chip and the second system-on-chip. The first system-on-chip and the second system-on-chip respectively forward the first memory request and the second memory request to one of a plurality of memories including the first memory and the second memory according to the first device address and the second device address.

Abstract: A hub chiplet includes a functional module. The hub chiplet includes a top connection module formed on a cross-section of the hub chiplet in a first direction; a bottom connection module formed on a cross-section of the hub chiplet in a second direction opposite to the first direction; a left connection module formed on a cross-section of the hub chiplet in a third direction perpendicular to a first straight line connecting the top connection module to the bottom connection module; and a right connection module formed on a cross-section of the hub chiplet in a fourth direction that is perpendicular to the first straight line and is opposite to the third direction. The top connection module is connectable to the bottom connection module through a device-to-device (D2D) connection, and the left connection module is connectable to the right connection module through the D2D connection.

Abstract: A semiconductor device includes a first processor configured to generate a first memory physical address and a first memory request; a second processor configured to generate a second memory physical address and a second memory request; a first system-on-chip physically connected to the first processor and configured to convert the first memory physical address into a first device address; a second system-on-chip physically connected to the second processor and the first system-on-chip and configured to convert the second memory physical address into a second device address; and a first memory and a second memory respectively and physically connected to the first system-on-chip and the second system-on-chip. The first system-on-chip and the second system-on-chip respectively forward the first memory request and the second memory request to one of a plurality of memories including the first memory and the second memory according to the first device address and the second device address.