Abstract: A testing circuit and method for thin film transistor display array, for testing the yield of a thin film transistor array is provided. The testing circuit includes an array tester, a test panel (DUT) and a sense amplifier array. The sense amplifier is composed of a plurality of trans-impedance amplifier units and a plurality of parasitic capacitance discharge circuit units. Every sense amplifier includes a trans-impedance amplifier, which is implemented by an operational amplifier, two switches and an operation capacitance. The trans-impedance amplifier is used to form an integrated circuit and the output is transmitted to a sampling/hold circuit via a switch. Also included is a parasitic capacitance discharge circuit that is used to form a discharge route for the charge of the parasitic capacitance.