Abstract: An electrostatic discharge protection device is disclosed. The electrostatic discharge protection device preferably includes a first transistor, a second transistor, and an electrostatic discharge clamping circuit. The first transistor includes a first drain electrically connected to an input/output pin of a chip, a first source electrically connected to a first voltage input pin of the chip, and a first gate. The first drain is preferably an internally shrunk drain. The second transistor includes a second drain electrically connected to the input/output pin of the chip, a second source electrically connected to a second voltage input pin and a second gate. The electrostatic discharge clamping circuit is electrically connected to the first voltage input pin and the second voltage input pin.

Abstract: A drive circuit of a displayer for driving at least a pixel, including: an output stage coupled to the pixel and controlled by a pixel signal to switch an output voltage on the pixel; a calibration device coupled between the output stage and the pixel and including an input end controlled by a bias voltage further calibrating the brightness of the pixel; a stabilizing device coupled between the input end of the calibration device and the pixel signal for stabilizing the voltage on the input end of the calibration device to be at the level of the bias voltage after a variation; and a accelerating device coupled between the stabilizing device and a voltage source for generating the bias voltage and accelerating the speed stabilizing the voltage on the input end of the calibration device to be at the level of the bias voltage.

Abstract: In an adjustable voltage examining module, while a logic tester issues an input signal to an audio module under test, upper/low-threshold reference signals are simultaneously issued to an adjustable voltage comparing circuit. While the adjustable voltage comparing circuit receives a signal under test returned by the to-be-examined audio module after a while, the adjustable voltage comparing circuit loads both an high-threshold reference voltage and a low-threshold reference voltage respectively indicated by the reference upper/low-threshold signal so as to compare both the upper and low-threshold reference voltages with the signal under test. Therefore, while the signal under test is examined to acquire a voltage level between voltage levels of the upper and low-threshold reference signals, precise operations of the audio module under test are assured, and time wasted by continuously-issued interrupt is saved.

Abstract: A circuit testing apparatus for testing a device under test is disclosed. The device under test includes a first terminal end and second terminal end for generating a first output signal and a second output signal, respectively. The circuit testing apparatus determines whether the device under test has passed the test according to the first and second output signals.

Abstract: An error-correcting method used in decoding data transmission is disclosed. The error-correcting method is used for analyzing an error receiving data received from a receiving terminal and comprises: providing a first calculating formula for manipulation of the receiving data to generate the first sum; providing a second calculating formula for manipulation of the receiving data to generate the second sum; identifying the error position of the receiving data according to the result of dividing the second sum by the first sum.

Abstract: A drive circuit of a carbon nanotube display (CNDP) used to drive at least a pixel of a CNDP is provided, having an output stage and a calibration device. The output stage is coupled to the pixel and controlled by a pixel signal to switch the pixel between a high voltage and a low voltage. The calibration device is coupled between the output stage and the pixel and controlled by a bias to calibrate the equivalent resistance of the calibration device and further calibrate the brightness of the pixel.

Abstract: The audio processing system disclosed in the invention comprises an audio processor and an audio amplifier. The audio processor receives a data signal to generate a processed signal, and comprises at least one gain control circuit and at least one operational amplifier. The gain control circuit generates a gain signal according to a volume control signal, a reference signal, and a feedback signal. The operational amplifier couples to the gain control circuit and amplifies the data signal by the gain signal to generate a processed signal. The audio amplifier couples to the audio processor to receive and amplify the processed signal, wherein an amplified signal is generated.

Abstract: A motor driving circuit has a motor operated with a forward operation, a reverse operation, an inactivating operation, and/or a brake operation under a constant current mode, a constant voltage mode, and/or a full swing mode. The motor driving circuit also prevents usage of multiple operational amplifiers and errors brought by the usage of the multiple operational amplifiers with simple circuit designs.

Abstract: An electrostatic discharge (ESD) protection circuit having first and second transistors and an ESD clamp circuit. The first and second transistors are coupled in series between first and second voltage input pins of a chip. The ESD clamp circuit is coupled between the first and second voltage input pins. The drains of the first and second transistors are coupled to an I/O pin of the chip. The doping regions of the first and second transistors are of distinct doping concentrations. The first transistor comprises four doping regions, and has a source formed by the first and third doping regions, and has a drain formed by the second and the fourth doping regions. The first doping region is within the third doping region. The second doping region is within the fourth doping region. The doping concentration of the fourth doping region is less than that of the third doping concentration.

Abstract: An amplifier circuit includes a modulation signal generating circuit, a driving stage circuit and an output stage circuit. The modulation signal generating circuit generates a pair of modulation signals according to a pair of differential input signals and a pair of clock signals. The pair of clock signals includes a first clock signal and a second clock signal having a phase difference therebetween. The driving stage circuit generates a pair of driving signals according to the pair of modulation signals. The output stage circuit generates a pair of amplified output signals according to the pair of driving signals.

Abstract: An image identification apparatus for comparing an image frame with a predetermined image is disclosed. The image identification apparatus includes a transformation module, a first comparing module, a second comparing module and a determination module. The transformation module is used for transforming the predetermined image to a predetermined image data and transforming the image frame to a first image data. The first comparing module and the second comparing module are used for comparing the predetermined image data with the first image information and generating a first comparing result and a second comparing result. The determination module is used for determining the comparing result of the image frame and the predetermined image according to the first comparing result and the second comparing result.

Abstract: An image display device includes a timing controller capable of overdriving. The timing controller has three line buffers, an image reverse processing unit, and an overdrive unit. The first line buffer buffers first line data of a second frame, wherein the second frame is generated later than a first frame. The second line buffer buffers first compressed data. The image reverse processing unit estimates first and second line data of the first frame according to the first compressed data. According to the first and second line data of the first and second frames, the overdrive unit outputs first and second lines of interleaving data for an interleaving frame. The interleaving frame is inserted between the first and second frames. With the third line buffer, the timing controller outputs the first and second lines of interleaving data at different time point.

Abstract: By classifying an electro-phoretic display integrated circuit (EPD IC) into a digital routine module, a digital non-routine module, and an analog routine module, and by switching off the digital non-routine module and the analog routine module, power consumption of the EPD IC may be effectively reduced, and an available time of an integrated circuit card utilizing the EPD IC may also be lengthened.

Abstract: A one-shot circuit capable of being integrated into a chip generates a frequency-dividing signal according to a reference clock signal of a clock signal generator by means of a frequency-dividing circuit. In this way, the order of the magnitude of the cycle length of the frequency-dividing signal can be raised up by increasing the frequency-dividing times in the frequency-dividing circuit, so that the resistance and the capacitance of an RC oscillator of the clock signal generator are effectively reduced. Therefore, the circuited area occupied by the RC oscillator of the clock signal generator is reduced, so that the one shot circuit can be integrated into a chip without increasing the cost.

Abstract: A driving circuit includes a dead-time detecting circuit, a duty-cycle controlling circuit, and a switch controlling circuit. The dead-time detecting circuit is coupled to an output of a power switch set for detecting a switching voltage on the output of the power switch set and accordingly outputting a dead-time detecting signal. The output of the power switch set is coupled to the first end of an inductive load, and the second end of the inductive load provides an output voltage. The duty-cycle controlling circuit is coupled to the second end of the inductive load for generating a set/reset signal according to the output voltage. The switch controlling circuit controls the power switch set to be away from a dead state according to the set/reset signal and the dead-time detecting signal.

Abstract: The invention provides a handler and a method for testing the same. The handler comprises a sorter and a testing module. The testing module further comprises a signal generator, a sensor, and a signal comparator. The signal generator generates and sends out a first handling signal. The sorter receives the first handling signal and correspondingly places a first electronic component on a first region according to the first handling signal. The sensor senses the first electronic component on the first region, and then correspondingly generates and sends out a second handling signal. The signal comparator is electrically connected to the sensor and the signal generator, and receives the first handling signal and the second handling signal. The signal comparator determines whether the first handling signal is equivalent to the second handling signal, and correspondingly sends out a comparing signal.

Abstract: General speaking, a resistor of high resistivity has a negative-temperature-coefficient and a resistor of low resistivity has a positive-temperature-coefficient. Utilizing this characteristic, an appropriate proportion between the above resistors can be found to make a combined resistor with an approximate zero-temperature-coefficient. The combined resistor can be used to design a circuit for generating voltage and current with approximate zero-temperature-coefficients.

Abstract: A beat frequency cancellation circuit, for an amplifier, includes a coupling device connected between two signal processing paths of the amplifier for compensating for beat frequency effects of output signals between the signal processing paths.

Abstract: Dead-time detector includes an N-type power switch and a resistor. The N-type power switch includes a first end coupled to the output end of the output-stage circuit for receiving an output voltage, a second end for outputting a dead-time detecting signal, and a control end for receiving a gate-controlling voltage. The resistor is coupled between the second end of the N-type power switch and a voltage source providing a high voltage for keeping the voltage of the dead-time detecting signal when the N-type power switch does not output the dead-time detecting signal representing “ON”. When the output voltage is so lower than the gate-controlling voltage that the N-type power switch is turned on, the N-type power switch outputs the dead-time detecting signal representing “ON”. When the dead-time detecting signal represents “ON”, the output-stage circuit leaves the dead-time state.

Abstract: An oscillation circuit including a first transistor, a second transistor, a current source, a first inverter, and an impedance unit is disclosed. The first transistor has a first source receiving a first operation voltage, a first drain, and a first gate coupled to the first drain. The second transistor has a second source receiving the first operation voltage, a second drain, and a second gate coupled to the first gate. The current source is coupled between the first drain and a grounding voltage. The first inverter generates an oscillation signal and has a first input terminal, a first output terminal, and a first power terminal coupled to the second drain. The impedance unit is coupled between the first input terminal and the first output terminal.