Abstract: A semiconductor chip carrier and contact array package having an apertured dielectric bottom layer (11), one or more chip connection layers such as wire bond layers (16, 17) insulated from one another, at least one chip-holding recess (24) in the wire bond layers and a heat conductive copper heat sink insert (26) extending across the aperture of the dielectric layer and forming a base adapted to be in heat-conductive contact with the bottom of an integrated circuit chip (27) to be attached thereon whereby heat flux generated by the chip is quickly and efficiently removed from the chip body. The wire bond layers (16, 17) contains metallization patterns (29) for bonding to the chip and a grid array of contacts or connection pins (20) connected to plated through-holes in the wire bond layer(s) for plugging the carrier to a circuit board or the like.

Abstract: A cap and seal including a central cap (20) to be positioned over an electronic component such as an integrated circuit chip (12), has a spaced upstanding wall or dam (22) which may be staked to the circuit board in assembly forming with the peripheral side wall (21) of the cap a channel or moat (19). Bridging means (24) extend between wall (21) and wall (22) onto which is placed a preform ring (30) of solid sealant material. Heating of the assembly, more particularly ring (30), allows melted sealant material to flow under and around bridging means (24) to form a confined seal between wall (21), wall (22) and an annular surface (29) on the circuit board surrounding cap wall (21).

Abstract: Method and apparatus to test continuity of miniature printed circuit board traces prior to installation of components. A short circuits probe and an open circuits probe are each provided which are specific to the pattern of traces to be tested. The probes are constructed by adapting a mirror image of the traces to be tested as probe contact points and registering the adapted mirror image as plating on a second circuit board substrate. Interconnections between contact points are typically provided on the back side of the second substrate. The interconnections couple the contact points with a continuity indicator. The circuit pattern specific probes according to the invention are employed by aligning the contact points with the circuit board traces to be tested and then effecting contact therebetween. The plating forming the contact points is of sufficient uniformity and elevation to provide desired clearance between adjacent traces.