Abstract: The disclosed protocol analyser (100) decodes and analyse PCIe signals between a host node (102) and a device node (104), the signals being routed through an interposer (106). The analyser comprises at least a pair of high data rate 1:3 fanout buffers (108). The signals from the interposer are fed to the buffers (108) to obtain three copies of the signals. Three transceivers (110a, 110b, 110c) receive the signals from the fanout buffers and each of them samples one of the three copies of the signals. A link training and status state machine decoder (112) detects a speed or a change in speed in the PCIe signals. Based on the detected speed it selects one of the tapped signals, for protocol decoding and analysis. A protocol analyser logic block (114) analyses one of the copies of the signals conforming to the relevant PCIe protocols, from Gen1 to Gen6.

Abstract: An FPGA based system for decoding PAM-3 signals is disclosed, wherein the system comprises a directional coupler for separating 100BASE-T1 and 1000BASE-T1 master and slave signals, DVGAs for amplifying the master and slave signals, ADCs for sampling the amplified signals, and a FPGA module, wherein the FPGA module is configured for decoding the PAM-3 symbols, in real-time, from oversampled ADCs data using fully pipelined Register Transfer Level (RTL) architecture.

Abstract: An FPGA based system for decoding PAM-3 signals is disclosed, wherein the system comprises a directional coupler for separating 100BASE-T1 and 1000BASE-T1 master and slave signals, DVGAs for amplifying the master and slave signals, ADCs for sampling the amplified signals, and a FPGA module, wherein the FPGA module is configured for decoding the PAM-3 symbols, in real-time, from oversampled ADCs data using fully pipelined Register Transfer Level (RTL) architecture.