Abstract: A compressed memory address parity (CMAP) checking apparatus for checking the parity of data read from a data memory comprising a low capacity auxiliary memory with 2.sup.N address spaces and an adaptive auxiliary memory addressing scheme to reduce the amount of memory required to perform parity checking. When data is stored in the data memory at an address MA having M bits, (M-N) bits of the data memory address together with one or more parity bits generated from the data stored in the data memory is stored in the auxiliary memory at an address given by the remaining N bits of the data memory address. When data is read from an address MA in the data memory, the (M-N) bits at the address N in the auxiliary memory is compared with the corresponding (M-N) bits in the data memory address. If there is a match, the one or more parity bits stored in the auxiliary memory are read.