Abstract: A memory device includes a memory array, a first protocol circuit, a second protocol circuit, an operation interface, and a protocol detection circuit. The first protocol circuit, which implements a first communication protocol, and the second protocol circuit, which implements a second communication protocol, are coupled in parallel between the memory array and the operation interface. The protocol detection circuit, which is coupled to the operation interface and to the first and second protocol circuits, monitors control signals provided to the operation interface by a host controller to determine which communication protocol the host controller employs. In response thereto, the protocol detection circuit selects one of the first and second protocol circuits to handles communication between the host controller and the memory device.

Abstract: A switching circuit includes a switch having first and second terminals coupled between a voltage supply and ground potential and having a control terminal coupled to receive a control signal indicative of the output voltage of an associated semiconductor circuit. The switch also includes an output terminal coupled to the well region within which is formed the associated semiconductor circuit. In preferred embodiments, the control signal transitions from a first state to a second state when the output voltage exceeds a predetermined potential. In response thereto, the switching circuit changes the well potential of the associated semiconductor circuit from a first voltage to ground potential, wherein the first voltage is greater than ground potential.

Abstract: A switching circuit includes a first switch connected between a first node and a first potential, a second switch connected between the first node and a second potential levels, a third switch connected between the first node and an output terminal, and a fourth switch connected between the output terminal and a third potential. A first control signal controls the conductivity of the first and second switches, a second control signal controls the conductivity of the third switch, and a logical combination the first and second control signals controls the conductivity of the fourth switch.

Abstract: A nonvolatile memory array is disclosed which includes a plurality of PMOS two-transistor (2T) memory cells. Each 2T cell includes a PMOS floating gate transistor and a PMOS select transistor and is connected between a bit line and a common source line. The select gate and the control gate of each 2T cell in a common row are connected to a word line and to a control gate line, respectively. The 2T cells of the array are programmed using a combination of FN tunneling and BTBT induced hot electron injection, and are erased using FN tunneling. In some embodiments, the array is divided into sectors, where each sector is defined by an n- well region and includes a predetermined number of rows of the 2T cells. Here, the source of each 2T cell in a sector is coupled to a common source line of the sector. In other embodiments, the bit lines of the array are segmented along sector boundaries.

Abstract: A charge pump circuit including N stages of diode-capacitor voltage multipliers clocked so as to convert a low voltage received from a supply voltage to a high voltage at an output terminal thereof employs an output stage to improve the efficiency of the charge pump. The output stage includes first and second legs each coupled to the output terminal, where the first leg provides current to the output terminal during low transitions of the clock signal and the second leg provides current to the output terminal during high transitions of the clock signal. In some embodiments, numerous ones of the above-mentioned charge pump circuit may be connected in parallel to achieve even greater output currents. Thus, unlike conventional charge pump circuits, a substantially constant current is provided to the output terminal throughout each period of the clock signal, thereby increasing the average total current provided to the output terminal and, thus, increasing the driving capability of the charge pump circuit.

Abstract: The frequency of a clocking signal is adjusted in response to fluctuations in the power supply voltage. In one embodiment, a control circuit has a plurality of clock input terminals each coupled between selected adjacent ones of the stages of a multiple-stage ring oscillator circuit and has an output clock terminal coupled to an input terminal of the ring oscillator circuit. In this manner, the control circuit may implement a plurality of loops each including a different variety of the stages of the ring oscillator circuit, wherein the clocking signal associated with each of the loops has a unique frequency. A plurality of trip voltages each being equal to a unique predetermined fraction of the power supply voltage are compared to a reference voltage. The control circuit selects, in response to the comparison of the trip voltages and the reference voltage, one of the loops mentioned above to provide its clocking signal to an output terminal of the oscillator.

Abstract: A semiconductor fabrication process allows for the fabrication of high-voltage transistors, logic transistors, and memory cells where, as required for sub-0.3 micron device geometries, the gate oxide of the logic transistors is thinner than the tunnel oxide thickness of the non-volatile memory cells without the undesirable contamination of the gate oxide of the logic transistors or contamination of the tunnel oxide of the memory cells. In one embodiment, the tunnel oxide of the memory cells is grown to a desired thickness. In a next step, a layer of doped polysilicon which will serve as the floating gate of the memory cell(s) is immediately deposited over the tunnel oxide of the memory cells, thereby protecting the tunnel oxide from contamination in subsequent masking and etching steps. The gate oxide of the logic transistors and the gate oxide of the high-voltage transistors are then grown to a desired thickness.

Abstract: A negative voltage level translator includes an output terminal which is electrically connected to a word line of the associated memory array. The voltage level of the output terminal, and thus the voltage level of the associated word line, is controlled by a cross-coupled latch. If the word line associated with the negative voltage level translator has been selected during erasing, the cross-coupled latch enters a first state which results in the output terminal being pulled to a negative erase voltage. This negative erase voltage, which may be generated by a negative charge pump, is in this manner coupled to the control gates of the array's selected memory cells to cause the erasing of such memory cells via, for instance, electron tunneling. If the word line associated with the output terminal has not been selected for erasing, the cross-coupled latch enters a second state which results in the output terminal being maintained at a floating potential.

Abstract: A pulse ramp control circuit allows for the program voltage applied to the control gate of a memory cell to be ramped from a low voltage to a high voltage in a precise manner. The ramp rate of this program voltage is primarily determined by a single capacitor and the bias current provided thereto. By providing a ramped program voltage to the memory array during programming operations, present embodiments effectively cover the entire distribution of program voltage v. program current for the memory cells to be programmed, thereby minimizing over-program and under-program conditions without reducing program time.

Abstract: A charge pump circuit including N stages of diode-capacitor voltage multipliers clocked so as to convert a low voltage received from a supply voltage to a high voltage at an output terminal thereof employs an output stage to improve the efficiency of the charge pump. The output stage includes first and second legs each coupled to the output terminal, where the first leg provides current to the output terminal during low transitions of the clock signal and the second stage provides current to the output terminal during high transitions of the clock signal. In some embodiments, the numerous one of the above-mentioned charge pump circuit may be connected in parallel to achieve even greater output currents. Thus, unlike conventional charge pump circuits, a substantially constant current is provided to the output terminal throughout the period of the clock signal, thereby increasing the average total current provided to the output terminal and, thus, increasing the driving capability of the charge pump circuit.

Abstract: A NAND Flash EEPROM string is formed in a common N-well and includes a plurality of P-channel MOS stacked-gate storage transistors and P-channel MOS string and ground select transistors. In the preferred embodiment, each P-channel storage transistor is programmed via hot electron injection from the depletion region proximate its P+ drain/N-well junction and erased via electron tunneling from its floating gate to its P-type channel as well as to its P+ source and P+ drain regions without requiring high programming and erasing voltages, respectively. Further, high P/N junction biases are not required during programming or erasing operations. This allows the dimensions of the present embodiments to be reduced to a size smaller than that of comparable conventional N-channel NAND Flash EEPROM strings.