Abstract: A negative differential resistance (NDR) field-effect transistor element is disclosed, formed on a silicon-based substrate using conventional MOS manufacturing operations. Methods for improving a variety of NDR characteristics for an NDR element, such as peak-to-valley ratio (PVR), NDR onset voltage (VNDR) and related parameters are also disclosed.

Abstract: A negative differential resistance (NDR) field-effect transistor element is disclosed, formed on a silicon-based substrate using conventional MOS manufacturing operations. Methods for improving a variety of NDR characteristics for an NDR element, such as peak-to-valley ratio (PVR), NDR onset voltage (VNDR) and related parameters are also disclosed.

Abstract: A variety of processes are disclosed for controlling NDR characteristics for an NDR element, such as peak-to-valley ratio (PVR), NDR onset voltage (VNDR) and related parameters. The processes are based on conventional semiconductor manufacturing operations so that an NDR device can be fabricated using silicon based substrates and along with other types of devices.

Abstract: An active negative differential resistance element (an NDR FET) and a memory device (such as an SRAM) using such elements is disclosed. Soft error rate (SER) performance for NDR FETs and such memory devices are enhanced by adjusting a location of charge traps in a charge trapping layer that is responsible for effectuating an NDR behavior. Both an SER and a switching speed performance characteristic can be tailored by suitable placement of the charge traps.

Abstract: An enhanced method of writing and reading a memory device, such as an SRAM using negative differential resistance (NDR) elements), is disclosed. This is done through selective control of biasing of the active elements in a memory cell. For example in a write operation, a memory cell is placed in an intermediate state to increase write speed. In an NDR based embodiments, this is done by reducing a bias voltage to NDR FETs so as to weaken the NDR element (and thus disable an NDR effect) during the write operation. Conversely, during a read operation, the bias voltages are increased to enhance peak current (as well as an NDR effect), and thus provide additional current drive to a BIT line. Embodiments using such procedures achieve superior peak to valley current ratios (PVR), read/write speed, etc.

Abstract: A silicon-on-insulator (SOI) memory device (such as an SRAM) using negative differential resistance (NDR) elements is disclosed. Body effect performances for NDR FETs (and other FETs) that may be used in such device are enhanced by floating a body of some/all the NDR FETs.

Abstract: A negative differential resistance device is disclosed which is particularly suited as a replacement for conventional pull-up and load elements such as NDR diodes, passive resistors, and conventional FETs. The NDR device includes a charge trapping layer formed at or extremely near to an interface between a substrate (which can be silicon or SOI) and a gate insulation layer. The NDR device can be shut off during static operations to further reduce power dissipation.

Abstract: A silicon-on-insulator (SOI) memory device (such as an SRAM) using negative differential resistance (NDR) elements is disclosed. Body effect performances for NDR FETs (and other FETs) that may be used in such device are enhanced by floating a body of some/all the NDR FETs.

Abstract: An active negative differential resistance element (an NDR FET) and a memory device (such as an SRAM) using such elements is disclosed Soft error rate (SER) performance for NDR FETs and such memory devices are enhanced by adjusting a location of charge traps in a charge trapping layer that is responsible for effectuating an NDR behavior. Both an SER and a switching speed performance characteristic can be tailored by suitable placement of the charge traps.

Abstract: A charge trapping device, and a method of forming the same is disclosed. Charge traps are optimally distributed through a trapping region based on controlling various conventional processing operations, such as an implant, an anneal, an insulator film deposition, and the like. In some embodiments, FETs can be configured to include a negative differential resistance (NDR) characteristic when they utilize a particular charge trap energy and distribution.

Abstract: An enhanced method of writing and reading a memory device, such as an SRAM using negative differential resistance (NDR) elements), is disclosed. This is done through selective control of biasing of the active elements in a memory cell. For example in a write operation, a memory cell is placed in an intermediate state to increase write speed. In an NDR based embodiments, this is done by reducing a bias voltage to NDR FETs so as to weaken the NDR element (and thus disable an NDR effect) during the write operation. Conversely, during a read operation, the bias voltages are increased to enhance peak current (as well as an NDR effect), and thus provide additional current drive to a BIT line. Embodiments using such procedures achieve superior peak to valley current ratios (PVR), read/write speed, etc.

Abstract: A method of controlling a negative differential resistance (NDR) element is disclosed, which includes altering various NDR characteristics during operation to effectuate different NDR modes. By changing biasing conditions applied to the NDR element (such as a silicon based NDR FET) a peak-to-valley ratio (PVR) (or some other characteristic) can be modified dynamically to accommodate a desired operational change in a circuit that uses the NDR element. In a memory or logic application, for example, a valley current can be reduced during quiescent periods to reduce operating power. Thus an adaptive NDR element can be utilized advantageously within a conventional semiconductor circuit.

Abstract: A method of testing/stressing a charge trapping device, such as a negative differential resistance (NDR) FET is disclosed. By operating/stressing a charge trap device during/after manufacture, a distribution of charge traps can be altered advantageously to improve performance.

Abstract: A two terminal, silicon based negative differential resistance (NDR) element is disclosed, to effectuate a type of NDR diode for selected applications. The two terminal device is based on a three terminal NDR-capable FET which has a modified channel doping profile, and in which the gate is tied to the drain. This device can be integrated through conventional CMOS processing with other NDR and non-NDR elements, including NDR capable FETs. A memory cell using such NDR two terminal element and an NDR three terminal is also disclosed.

Abstract: A semiconductor device including integrated insulated-gate field-effect transistor (IGFET) elements and one or more negative differential resistance (NDR) field-effect transistor elements, combined and formed on a common substrate. Thus, a variety of circuits, including logic and memory are implemented with a combination of conventional and NDR capable FETs. Because both types of elements share a number of common features, they can be fabricated with common processing operations to achieve better integration in a manufacturing facility.

Abstract: An active negative differential resistance element (an NDR FET) and a memory device (such as an SRAM) using such elements is disclosed. Soft error rate (SER) performance for NDR FETs and such memory devices are enhanced by adjusting a location of charge traps in a charge trapping layer that is responsible for effectuating an NDR behavior. Both an SER and a switching speed performance characteristic can be tailored by suitable placement of the charge traps.

Abstract: An improved MISFET is disclosed which is particularly suited as a replacement for conventional pull-up and load elements such as NDR diodes, passive resistors, and conventional FETs. The MISFET includes a charge trapping layer formed at or extremely near to an interface between a substrate (which can be silicon or SOI) and a gate insulation layer. In this fashion, charge traps can be optimized for extremely rapid trapping and de-trapping of charge because they are extremely close to a channel of hot carriers. The MISFET channel can be shut off during static operations to further reduce power dissipation, and can also be adapted to operate with negative differential resistance.

Abstract: A memory cell using both negative differential resistance (NDR) and conventional FETs is disclosed. A pair of NDR FETs are coupled in a latch configuration so that a data value passed by a transfer FET can be stored at a storage node. By exploiting an NDR characteristic, the memory cell can be implemented with fewer active devices. Moreover, an NDR FET can be manufactured using conventional MOS processing steps so that process integration issues are minimized as compared to conventional NDR techniques.

Abstract: A process for forming/configuring a device to include a negative differential resistance (NDR) characteristic is disclosed. In a FET embodiment, an NDR characteristic is implemented by incorporating a dynamic threshold voltage in such device. An onset point for the NDR characteristic is also adjustable during a manufacturing process to enhance the performance of an NDR device.

Abstract: An n-channel metal-insulator-semiconductor field-effect transistor (MISFET) that exhibits negative differential resistance in its output characteristic (drain current as a function of drain voltage) is disclosed. The MISFET includes a dynamically variable and reversible threshold voltage which is controlled by a source-drain bias. A channel region of the MISFET is doped so as to enhance an electric field associated with the source-drain bias, and thus cause charge carriers to tunnel out of the channel and into a trapping region. A net charge in the trapping region results from the source-drain bias which can be used as an additional control mechanism for conduction in the MISFET.