Abstract: An improved negative differential resistance field effect transistor (NDR-FET) is disclosed. The NDR FET includes a charge trapping layer formed at or extremely near to an interface between a substrate (which can be silicon or SOI) and a gate insulation layer. In this fashion, charge traps can be optimized for extremely rapid trapping and de-trapping of charge because they are extremely close to a channel of hot carriers. The NDR-FET is also useable as a replacement for conventional NDR diode and similar devices in memory cells, and enables an entire family of logic circuits that only require a single channel technology (i.e., instead of CMOS) and yet which provide low power.