Abstract: A testing system including a plurality of ports, at least one controller, and a programmable memory. The plurality of ports may be adapted to implement an IEEE 1149.x standard interface. The at least one controller may be in electronic communication with at least one of the plurality of ports. The programmable memory may be in electrical communication with the at least one controller and adapted to store at least one clock forming variable. The at least one controller may be adapted to form an IEEE 1149.x clock signal for at least one of the plurality of ports based on the at least one clock forming variable. The at least one controller controls the IEEE 1149.x clock signal for at least one of the plurality of ports independently of the IEEE 1149.x clock signal for any other of the plurality of ports.

Abstract: A testing system including a plurality of ports, at least one controller, and a programmable memory. The plurality of ports may be adapted to implement an IEEE 1149.x standard interface. The at least one controller may be in electronic communication with at least one of the plurality of ports. The programmable memory may be in electrical communication with the at least one controller and adapted to store at least one clock forming variable. The at least one controller may be adapted to form an IEEE 1149.x clock signal for at least one of the plurality of ports based on the at least one clock forming variable. The at least one controller controls the IEEE 1149.x clock signal for at least one of the plurality of ports independently of the IEEE 1149.x clock signal for any other of the plurality of ports.