Patents Assigned to ProMOS Tech., Inc.
  • Patent number: 6365485
    Abstract: An improved method for forming a buried plate in a bottle-shaped deep trench capacitor. The method includes the steps of: (a) forming a deep trench into a semiconductive substrate; (b) filling the deep trench with a first dielectric material to a first predetermined depth; (c) forming a silicon nitride sidewall spacer in the deep trench above the dielectric layer; (d) removing the first dielectric layer, leaving the portion of the substrate below the sidewall spacer to be exposed; (e) using the sidewall spacer as a mask, causing the exposed portion of the substrate to be oxidized, then removing the oxidized substrate; (f) forming an arsenic-ion-dope conformal layer around the side walls of the deep trench, including the sidewall spacer; (g) heating the substrate to cause the arsenic ions to diffuse into the substrate in the deep trench not covered by the sidewall spacer; and (h) removing the entire arsenic-ion-doped layer.
    Type: Grant
    Filed: April 19, 2000
    Date of Patent: April 2, 2002
    Assignees: Promos Tech., Inc,, Mosel Vitelic Inc., Siemens Ag.
    Inventors: Jia. S. Shiao, Wen B. Yen
  • Patent number: 6187650
    Abstract: A method of forming a planar silicon nitride layer is disclosed. The method comprises: forming a pad oxide layer; forming a first nitride layer on the pad oxide layer; forming a stop layer on the first nitride layer; forming a second nitride layer on the stop layer; performing intermediate processes that damage the second nitride layer; removing the second nitride layer; removing the stop layer such that the first nitride layer remains as the planar silicon nitride layer.
    Type: Grant
    Filed: November 5, 1999
    Date of Patent: February 13, 2001
    Assignees: ProMOS Tech., Inc., Mosel Vitelic Inc., Infineon Tech. Inc.
    Inventors: Joseph Wu, Sheng-Fen Chiu, J. S. Shiao
  • Patent number: 6146987
    Abstract: A method for forming a contact plug that lands on a metal line of an interconnect structure formed on a semiconductor substrate. First, a first insulating layer is formed atop the substrate and between gaps in the interconnect structure. Next, an etching stop layer is formed on the first insulating layer. A second insulating layer is formed atop the etching stop layer. The second insulating layer is patterned and etched, stopping at the etching stop layer, to form a contact opening. The portion of the etching stop layer left exposed by the contact opening is removed. Finally, a barrier metal layer is formed along the walls of the contact opening and a conducting layer is deposited into the contact opening.
    Type: Grant
    Filed: August 25, 1999
    Date of Patent: November 14, 2000
    Assignees: ProMOS Tech., Inc., Mosel Vitelic, Inc., Siemens AG
    Inventors: Chien-chun Wang, Eddie Chiu, Chung-Yi Chen, Hsien-Yuan Chang