Patents Assigned to ProPlus Design Solutions, Inc.
  • Patent number: 9031825
    Abstract: Method and system are disclosed for statistical circuit simulation. In one embodiment, a computer implemented method for statistical circuit simulation includes providing descriptions of a circuit for simulation, wherein the descriptions include variations of statistical parameters of the circuit, partitioning the circuit into groups of netlists according to variations of statistical parameters of the circuit, simulating the groups of netlists using a plurality of processors in parallel to generate a plurality of output data files, and storing the plurality of output data files in a memory. The method of partitioning the circuit into groups of netlists includes forming the groups of netlists to be simulated in a single instruction multiple data environment, and forming the groups of netlists according to proximity of variations of statistical parameters of the circuit.
    Type: Grant
    Filed: April 2, 2012
    Date of Patent: May 12, 2015
    Assignee: Proplus Design Solutions, Inc.
    Inventor: Bruce McGaughy
  • Patent number: 8260600
    Abstract: Method and system are disclosed for simulating a circuit. The method includes representing a circuit using a matrix that represents a set of linear equations to be solved, identifying a delta matrix, which is a subset of the matrix that changed states from a previous time step to a current time step, computing an update of the delta matrix using a matrix decomposition approach, generating a current state of the matrix using a previous state of the matrix and the update of the delta matrix, and storing the current state of the matrix in a memory device.
    Type: Grant
    Filed: October 4, 2008
    Date of Patent: September 4, 2012
    Assignee: Proplus Design Solutions, Inc.
    Inventors: Linzhong Deng, Bruce McGaughy
  • Patent number: 7979814
    Abstract: Model evaluation and circuit simulation/verification is performed in a graphical processing unit (GPU). A multitude of first texture data corresponding to size parameters of devices are stored. A multitude of second texture data corresponding to instance parameters of the devices are stored. A multitude of third texture data corresponding to models of the devices are stored. A multitude of fourth texture data corresponding to terminal voltages received by the device are stored. A multitude of links linking each device instance to an associated device model, size parameters and instance parameters are stored. A quad having a size defined by the multitude of links is drawn by the quad in the GPU. Each thread in the quad is assigned to a different one of the multitude of links. The computations are carried out in each thread using the linked data to perform the model evaluation.
    Type: Grant
    Filed: March 12, 2008
    Date of Patent: July 12, 2011
    Assignee: ProPlus Design Solutions, Inc.
    Inventors: Yutao Ma, Yi Xu