Abstract: A method and a device for converting a first bus including at least a data wire and a clock wire into a single-wire bus, wherein a data bit of the first bus is converted on half a period of the clock signal for transmission over the second bus, a waiting pattern being placed on the second bus during the other half-period.
Type:
Grant
Filed:
July 14, 2009
Date of Patent:
April 17, 2012
Assignees:
STMicroelectronics (Rousset) SAS, Proton World Internationl N.V.