Patents Assigned to PROVINO TECHNOLOGIES, INC.
  • Procedures for improving efficiency of an interconnect fabric on a system on chip
    Patent number: 11003604
    Abstract: Optimizing transaction traffic on a System on a Chip (SoC) by using procedures such as expanding transactions and consolidating responses at nodes of an interconnect fabric for broadcasts, multi-casts, any-casts, source based routing type transactions, intra-streaming two or more transactions over a stream defined by a paired virtual channel-transaction class, trunking physical resources sharing common logical identifier, and using hashing to select among multiple physical resources sharing a common logical identifier.
    Type: Grant
    Filed: March 29, 2019
    Date of Patent: May 11, 2021
    Assignee: PROVINO TECHNOLOGIES, INC.
    Inventors: Shailendra Desai, Robert Totte, Juan Sierra, Parimal Gaikwad, Amit Jain, Mark Pearce
  • Arbitrating portions of transactions over virtual channels associated with an interconnect
    Patent number: 10853282
    Abstract: Arbitrating among portions of multiple transactions and transmitting a winning portion over one of a multiplicity of virtual channels associated with an interconnect on a clock cycle-by-clock cycle basis. By repeatedly performing the above each clock cycle, winning portions are interleaved and transmitted over the multiplicity of virtual channels over multiple clock cycles respectively.
    Type: Grant
    Filed: March 28, 2019
    Date of Patent: December 1, 2020
    Assignee: PROVINO TECHNOLOGIES, INC.
    Inventors: Shailendra Desai, Mark Pearce, Amit Jain, Rutul Bhatt
  • Arbitrating portions of transactions over virtual channels associated with an interconnect
    Patent number: 10838891
    Abstract: Arbitrating among portions of multiple transactions and transmitting a winning portion over one of a multiplicity of virtual channels associated with an interconnect on a clock cycle-by-clock cycle basis. By repeatedly performing the above each clock cycle, winning portions are interleaved and transmitted over the multiplicity of virtual channels over multiple clock cycles respectively.
    Type: Grant
    Filed: March 28, 2019
    Date of Patent: November 17, 2020
    Assignee: PROVINO TECHNOLOGIES, INC.
    Inventors: Shailendra Desai, Mark Pearce, Amit Jain, Rutul Bhatt
  • Procedures for implementing source based routing within an interconnect fabric on a system on chip
    Patent number: 10585825
    Abstract: Optimizing transaction traffic on a System on a Chip (SoC) by using procedures such as expanding transactions and consolidating responses at nodes of an interconnect fabric for broadcasts, multi-casts, any-casts, source based routing type transactions, intra-streaming two or more transactions over a stream defined by a paired virtual channel-transaction class, trunking physical resources sharing common logical identifier, and using hashing to select among multiple physical resources sharing a common logical identifier.
    Type: Grant
    Filed: March 29, 2019
    Date of Patent: March 10, 2020
    Assignee: PROVINO TECHNOLOGIES, INC.
    Inventors: Shailendra Desai, Robert Totte, Juan Sierra, Parimal Gaikwad, Amit Jain, Mark Pearce