Abstract: An electronic assembly heterogeneously integrates radio-frequency (RF) transistor chiplets into a host wafer, and the chiplets have interconnections to host wafer circuits. The assembly has at least one RF transistor chiplet having a chiplet circuit including a high-electron-mobility transistor (HEMT) or a heterojunction bipolar transistor (HBT). The host wafer has at least one host wafer circuit for the purpose of producing bias conditions that optimize performance of the HEMT or HBT. The host wafer circuit includes first circuitry to provide a DC bias of the HEMT or HBT; or second circuitry configured to sense radio-frequency operating conditions of the HEMT or HBT. The electrical interconnects are between the chiplet and the wafer, and electrically connect the host wafer circuit to the chiplet circuit.
Type:
Grant
Filed:
June 25, 2024
Date of Patent:
January 7, 2025
Assignee:
PseudolithIC, Inc.
Inventors:
James F. Buckwalter, Florian Herrault, Justin Kim, Michael Hodge, Daniel S. Green
Abstract: An electronic assembly has a backside capping layer, a host wafer having a back surface bonded to a top surface of the backside capping layer except for cavities in the wafer formed over areas of the backside capping layer, the cavities having side surfaces of the wafer. Chiplets have backsides bonded directly to at least portion of the areas of the top surface of the backside capping layer. A lateral dielectric material between side surfaces of the chiplets and side surfaces of the wafer, mechano-chemically bonds the side surfaces of the chiplets to the side surfaces of the wafer.
Type:
Grant
Filed:
June 12, 2023
Date of Patent:
October 22, 2024
Assignee:
PseudolithIC, Inc.
Inventors:
Florian Herrault, Isaac Rivera, Daniel S. Green, James F. Buckwalter
Abstract: An electronic assembly has a host wafer having a first circuit including wafer transistors and passive, non-transistor devices. Chiplets have a second circuit including at least one radio frequency (RF) transistor device. Electrical interconnects are between the chiplets and wafer. The electrical interconnects electrically connect the first circuit to the second circuits. Oscillators that have the wafer transistor, the RF transistor and the electrical interconnects produce a signal for built-in self-test circuits for testing an assembly design of the electronic assembly and speeds of the RF chiplet transistors.
Type:
Grant
Filed:
July 13, 2023
Date of Patent:
September 24, 2024
Assignee:
PseudolithIC, Inc.
Inventors:
James Buckwalter, Michael Hodge, Justin Kim, Daniel Green, Florian Herrault
Abstract: An electronic assembly has a host wafer having a first circuit including wafer transistors and passive, non-transistor devices. Chiplets have a second circuit including at least one radio frequency (RF) transistor device. Electrical interconnects are between the chiplets and wafer. The electrical interconnects electrically connect the first circuit to the second circuits. Oscillators that have the wafer transistor, the RF transistor and the electrical interconnects produce a signal for built-in self-test circuits for testing an assembly design of the electronic assembly and speeds of the RF chiplet transistors.
Type:
Grant
Filed:
July 13, 2023
Date of Patent:
March 26, 2024
Assignee:
PseudolithIC, Inc.
Inventors:
James Buckwalter, Michael Hodge, Justin Kim, Daniel Green, Florian Herrault
Abstract: An electronic assembly has a host wafer having a first circuit including passive devices for the purpose of one of tuning or matching networks. Chiplets are placed in the cavities. At least one chiplet has a second circuit including at least one transistor or switch device and passive tuning circuits including at least one of a stabilization network, a gain boosting network, a power delivery network, or a low-noise network. Electrical interconnects between the chiplets and wafer electrically connect the first circuitry to the second circuitry.
Type:
Grant
Filed:
March 10, 2023
Date of Patent:
November 7, 2023
Assignee:
PseudolithIC, Inc.
Inventors:
James Buckwalter, Michael Hodge, Justin Kim, Florian Herrault, Daniel Green
Abstract: An electronic assembly has a backside capping layer, a host wafer having a back surface bonded to a top surface of the backside capping layer except for cavities in the wafer formed over areas of the backside capping layer, the cavities having side surfaces of the wafer. Chiplets have backsides bonded directly to at least portion of the areas of the top surface of the backside capping layer. A lateral dielectric material between side surfaces of the chiplets and side surfaces of the wafer, mechano-chemically bonds the side surfaces of the chiplets to the side surfaces of the wafer.
Type:
Grant
Filed:
January 17, 2023
Date of Patent:
September 12, 2023
Assignee:
PseudolithIC, Inc.
Inventors:
Florian Herrault, Isaac Rivera, Daniel S. Green, James F. Buckwalter
Abstract: An electronic assembly has a host wafer having a first circuit including wafer transistors and passive, non-transistor devices. Chiplets have a second circuit including at least one radio frequency (RF) transistor device. Electrical interconnects are between the chiplets and wafer. The electrical interconnects electrically connect the first circuit to the second circuits. Oscillators that have the wafer transistor, the RF transistor and the electrical interconnects produce a signal for built-in self-test circuits for testing an assembly design of the electronic assembly and speeds of the RF chiplet transistors.
Type:
Grant
Filed:
March 27, 2023
Date of Patent:
August 22, 2023
Assignee:
PseudolithIC, Inc.
Inventors:
James Buckwaiter, Michael Hodge, Justin Kim, Daniel Green, Florian Herrault