Abstract: Circuitry for and a method of simulating neurons are disclosed. The circuitry for a neuron includes a synapse formed of two up/down counters and other logic circuitry. The counters combine to generate a four-bit number which represents the amplitude of the synaptic potential, which amplitude is increased upon receipt of an input pulse, and which decays over a period of time. If a fixer signal is received, representing an external event (which may be an output from other neurons), the decay will be halted, thereby fixing the synaptic potential at a different value.The output of the synapse is fed to a generator, which comprises counters and other logic circuitry for accumulating the received synapse output signals and which continuously counts back to a rest value, to thereby replicate the temporal summation capability of a neuron.When the value accumulated in the generator exceeds a threshold value, an output signal is generated, representing the firing of the neuron.