Patents Assigned to Pulsic Limited
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Patent number: 11853671Abstract: Vacant areas of a layer of an integrated circuit design are filled with shapes connected to the appropriate nets.Type: GrantFiled: June 8, 2021Date of Patent: December 26, 2023Assignee: Pulsic LimitedInventor: Graham Balsdon
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Patent number: 11748538Abstract: An automated analog layout tool creates not just one, but many electrically correct layouts from an input schematic. Designers can explore multiple layout options in a fraction of the time needed to produce just a single layout by hand. Because the tool produces layout results so quickly, parasitics are available for simulation early in the design process, further speeding the entire design cycle. The tool considers place and route concurrently.Type: GrantFiled: March 22, 2022Date of Patent: September 5, 2023Assignee: Pulsic LimitedInventors: Paul Clewes, Liang Gao, Jonathan Longrigg
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Patent number: 11281828Abstract: An automated analog layout tool creates not just one, but many electrically correct layouts from an input schematic. Designers can explore multiple layout options in a fraction of the time needed to produce just a single layout by hand. Because the tool produces layout results so quickly, parasitics are available for simulation early in the design process, further speeding the entire design cycle. The tool considers place and route concurrently.Type: GrantFiled: September 22, 2020Date of Patent: March 22, 2022Assignee: Pulsic LimitedInventors: Paul Clewes, Liang Gao, Jonathan Longrigg
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Patent number: 11200363Abstract: Simultaneous automatic placement and routing speeds up implementation an integrated circuit layout and improves the resulting layout such that the layout is more compact, has reduced parasitics, and has improved circuit performance characteristics (e.g., power, frequency, propagation delay, gain, and stability). A technique generates solutions based on random normalized polish expression, and includes cost considerations based on routing of interconnect.Type: GrantFiled: July 28, 2020Date of Patent: December 14, 2021Assignee: Pulsic LimitedInventors: Mark Waller, Paul Clewes, Liang Gao, Jonathan Longrigg
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Patent number: 11126779Abstract: A high-speed shape-based router is applicable to standard-cell digital designs, chip-level-block assembly designs, and other styles of design. In a flow of the invention, the technique establishes an initial structure for each net to be routed. Nets or parts of them are ordered. Each part of the net may be routed using a spine routing search, depth first search, or a space flood search, or any combination of these. Where sections fail or an error occurs, conflicts are identified, and the technique tries routing again.Type: GrantFiled: September 8, 2020Date of Patent: September 21, 2021Assignee: Pulsic LimitedInventor: Jeremy Birch
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Patent number: 11030374Abstract: Vacant areas of a layer of an integrated circuit design are filled with shapes connected to the appropriate nets.Type: GrantFiled: June 23, 2020Date of Patent: June 8, 2021Assignee: Pulsic LimitedInventor: Graham Balsdon
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Patent number: 10783292Abstract: An automated analog layout tool creates not just one, but many electrically correct layouts from an input schematic. Designers can explore multiple layout options in a fraction of the time needed to produce just a single layout by hand. Because the tool produces layout results so quickly, parasitics are available for simulation early in the design process, further speeding the entire design cycle. The tool considers place and route concurrently.Type: GrantFiled: May 23, 2016Date of Patent: September 22, 2020Assignee: Pulsic LimitedInventors: Paul Clewes, Liang Gao, Jonathan Longrigg
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Patent number: 10769343Abstract: A high-speed shape-based router is applicable to standard-cell digital designs, chip-level-block assembly designs, and other styles of design. In a flow of the invention, the technique establishes an initial structure for each net to be routed. Nets or parts of them are ordered. Each part of the net may be routed using a spine routing search, depth first search, or a space flood search, or any combination of these. Where sections fail or an error occurs, conflicts are identified, and the technique tries routing again.Type: GrantFiled: July 9, 2019Date of Patent: September 8, 2020Assignee: Pulsic LimitedInventor: Jeremy Birch
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Patent number: 10726184Abstract: Simultaneous automatic placement and routing speeds up implementation an integrated circuit layout and improves the resulting layout such that the layout is more compact, has reduced parasitics, and has improved circuit performance characteristics (e.g., power, frequency, propagation delay, gain, and stability). A technique generates solutions based on random normalized polish expression, and includes cost considerations based on routing of interconnect.Type: GrantFiled: April 10, 2018Date of Patent: July 28, 2020Assignee: Pulsic LimitedInventors: Mark Waller, Paul Clewes, Liang Gao, Jonathan Longrigg
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Patent number: 10691858Abstract: Vacant areas of a layer of an integrated circuit design are filled with shapes connected to the appropriate nets.Type: GrantFiled: September 19, 2017Date of Patent: June 23, 2020Assignee: Pulsic LimitedInventor: Graham Balsdon
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Patent number: 10346577Abstract: A high-speed shape-based router is applicable to standard-cell digital designs, chip-level-block assembly designs, and other styles of design. In a flow of the invention, the technique establishes an initial structure for each net to be routed. Nets or parts of them are ordered. Each part of the net may be routed using a spine routing search, depth first search, or a space flood search, or any combination of these. Where sections fail or an error occurs, conflicts are identified, and the technique tries routing again.Type: GrantFiled: January 26, 2016Date of Patent: July 9, 2019Assignee: Pulsic LimitedInventor: Jeremy Birch
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Patent number: 9940421Abstract: Simultaneous automatic placement and routing speeds up implementation an integrated circuit layout and improves the resulting layout such that the layout is more compact, has reduced parasitics, and has improved circuit performance characteristics (e.g., power, frequency, propagation delay, gain, and stability). A technique generates solutions based on a random normalized polish expression, and includes cost considerations based on routing of interconnect.Type: GrantFiled: October 10, 2011Date of Patent: April 10, 2018Assignee: Pulsic LimitedInventors: Mark Waller, Paul Clewes, Liang Gao, Jonathan Longrigg
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Patent number: 9767242Abstract: Vacant areas of a layer of an integrated circuit design are filled with shapes connected to the appropriate nets.Type: GrantFiled: June 4, 2013Date of Patent: September 19, 2017Assignee: Pulsic LimitedInventor: Graham Balsdon
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Patent number: 9245082Abstract: A high-speed shape-based router is applicable to standard-cell digital designs, chip-level-block assembly designs, and other styles of design. In a flow of the invention, the technique establishes an initial structure for each net to be routed. Nets or parts of them are ordered. Each part of the net may be routed using a spine routing search, depth first search, or a space flood search, or any combination of these. Where sections fail or an error occurs, conflicts are identified, and the technique tries routing again.Type: GrantFiled: June 21, 2006Date of Patent: January 26, 2016Assignee: Pulsic LimitedInventor: Jeremy Birch
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Patent number: 8966425Abstract: A technique generates small scale clock trees using a spine-based architecture (using spine routing) while also using clustered placement. Techniques are used to control clock sink cluster contents in order to minimize clock skew, minimize clock buffer count, and minimize use of routing resources. This approach also provides the user with ample structure and control to customize small efficient clock trees, and can also reduce clock power consumption.Type: GrantFiled: March 14, 2013Date of Patent: February 24, 2015Assignee: Pulsic LimitedInventors: Robert Eisenstadt, Mark Waller, Tim Parker, Mark Williams, Jeremy Birch, Graham Balsdon, Fumiako Sato
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Patent number: 8949760Abstract: A technique will automatically route interconnect of an integrated circuit and adjust spacing between tracks or interconnect in order to improve performance or reduce electromigration effects. By increasing spacing between certain tracks or moving tracks, performance can improve because a track will be more noise immunity from nearby tracks on the same layer or on different layers. The automatic router will adjust spacing between tracks depending on one or more factors. These factors may include current associated with a track, width of a track, capacitance, inductance, and electromigration. In a specific implementation, the technique uses a shape-based approach where a grid is not used. The technique may further vary the width of the tracks.Type: GrantFiled: January 9, 2012Date of Patent: February 3, 2015Assignee: Pulsic LimitedInventors: Jeremy Birch, Mark Waller, Graham Balsdon
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Patent number: 8788999Abstract: A system automatically routes interconnect of an integrated circuit design using variable width interconnect lines. For example, a first automatically routed interconnect may have a different width from a second automatically routed interconnect. The system will vary the width of the interconnect lines based on certain factors or criteria. These factors include current or power handling, reliability, electromigration, voltage drops, self-heating, optical proximity effects, or other factors, or combinations of these factors. The system may use a gridded or a gridless (or shape-based) approach.Type: GrantFiled: July 2, 2013Date of Patent: July 22, 2014Assignee: Pulsic LimitedInventors: Graham Baldsdon, Jeremy Birch, Mark Williams, Mark Waller, Tim Parker, Fumiaki Sato
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Patent number: 8751996Abstract: A system of automatically routing interconnect of a integrated circuit design while taking into consideration the parasitic issues of the wiring as it is created. The system will be able to select an appropriate wiring pattern so that signals meet their performance requirements.Type: GrantFiled: December 11, 2012Date of Patent: June 10, 2014Assignee: Pulsic LimitedInventors: Jeremy Birch, Mark Waller, Mark Williams, Graham Balsdon, Fumiaki Sato, Tim Parker
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Patent number: 8707239Abstract: An iterative technique is used to automatically route nets and alter spacing of an integrated circuit design to achieve a fully routed and compact result. After identifying solid and hollow channels, the technique automatically places route paths to connect pins of cells in the solid channels, where route paths may be placed within the solid channels or hollow channels. The technique can reduce a width of at least one hollow channel when an entire space of the hollow channel is not occupied by a placed route path.Type: GrantFiled: December 11, 2012Date of Patent: April 22, 2014Assignee: Pulsic LimitedInventor: Mark Waller
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Patent number: 8490036Abstract: A system and technique to specifies patterns to search for in an integrated circuit layout, and specifies proposed replacement patterns. A description file includes specifications for one or more patterns to be searched for. In the description file, for each pattern, there may be one or more proposed replacement patterns. The description file is read. Pattern matches, if any, in a layout are found. A proposed replacement pattern is tested in place of a matched pattern. If acceptable, the proposed pattern may be used to replace the matched pattern.Type: GrantFiled: January 18, 2010Date of Patent: July 16, 2013Assignee: Pulsic LimitedInventor: Mark Waller