Abstract: An enhanced DRAM contains embedded row registers in the form of latches. The row registers are adjacent to the DRAM array, and when the DRAM comprises a group of subarrays, the row registers are located between DRAM subarrays. When used as on-chip cache, these registers hold frequently accessed data. This data corresponds to data stored in the DRAM at a particular address. When an address is supplied to the DRAM, it is compared to the address of the data stored in the cache. If the addresses are the same, then the cache data is read at SRAM speeds. The DRAM is decoupled from this read. The DRAM also remains idle during this cache read unless the system opts to precharge or refresh the DRAM. Refresh or precharge occur concurrently with the cache read. If the addresses are not the same, then the DRAM is accessed and the embedded register is reloaded with the data at that new DRAM address.

Abstract: A method and device for hiding refresh operations during accesses to sub-arrays of a pseudo-static memory device. By refreshing sub-arrayj while filling the row Ri (where i?j) corresponding to sub-arrayi, refresh operations can be performed without risking that a read request will interrupt the refresh operation. Additional refresh operations of sub-arrayi can be performed serially with the operations of filling the row Ri without delaying the overall burst read or write operation if the burst is made sufficiently long.

Abstract: A method and device for hiding refresh operations during accesses to sub-arrays of a pseudo-static memory device. By refreshing sub-arrayj while filling the row Ri (where i?j) corresponding to sub-arrayi, refresh operations can be performed without risking that a read request will interrupt the refresh operation. Additional refresh operations of sub-arrayi can be performed serially with the operations of filling the row Ri without delaying the overall burst read or write operation if the burst is made sufficiently long.

Abstract: An enhanced DRAM contains embedded row registers in the form of latches. The row registers are adjacent to the DRAM array, and when the DRAM comprises a group of subarrays, the row registers are located between DRAM subarrays. When used as on-chip cache, these registers hold frequently accessed data. This data corresponds to data stored in the DRAM at a particular address. When an address is supplied to the DRAM, it is compared to the address of the data stored in the cache. If the addresses are the same, then the cache data is read at SRAM speeds. The DRAM is decoupled from this read. The DRAM also remains idle during this cache read unless the system opts to precharge or refresh the DRAM. Refresh or precharge occur concurrently with the cache read. If the addresses are not the same, then the DRAM is accessed and the embedded register is reloaded with the data at that new DRAM address.

Abstract: An SDRAM and method for operating it provide for increased data access speed. The SDRAM includes a central memory region with memory blocks arranged in sets on respective opposite sides. A plurality of primary sense amplifier sets are provided, each set being associated with a respective pair of the memory blocks and located adjacent thereto. A row cache is provided in the central memory region, and row decoders decode a row address in response to a “bank activate” command and move data from a decoded row address into a primary sense amplifier set associated with a memory block containing the decoded row address and into the row cache, prior to application of a “read” command to the SDRAM. Column decoders decode a column address in response to a “read” command and for reading data from the cache in accordance with the decoded column address.

Abstract: A method and device for hiding refresh operations during accesses to sub-arrays of a pseudo-static memory device. By refreshing sub-arrayj while filling the row Ri (where i?j) corresponding to sub-arrayi, refresh operations can be performed without risking that a read request will interrupt the refresh operation. Additional refresh operations of sub-arrayi can be performed serially with the operations of filling the row Ri without delaying the overall burst read or write operation if the burst is made sufficiently long.

Abstract: An SDRAM and method for operating it provide for increased data access speed. The SDRAM includes a central memory region with memory blocks arranged in sets on respective opposite sides. A plurality of primary sense amplifier sets are provided, each set being associated with a respective set of the memory blocks and located adjacent thereto. A row cache is provided in the central memory region, and row decoders decode a row address in response to a “bank activate” command and move data from a decoded row address into a primary sense amplifier set associated with a memory block containing the decoded row address and into the row cache, prior to application of a “read” command to the SDRAM. Column decoders decode a column address in response to a “read” command and for reading data from the cache in accordance with the decoded column address.