Abstract: A system of charging a battery pack with single charger includes a battery module, a main charging module, and a balance charging module. The battery module has a battery pack, and the battery pack has a plurality of cells in series. The main charging module has a main charger. The balance charging module has a balance charger. All the cells of the battery pack of the battery module are charged at the same time by the main charger of the main charging module. After the charging task of the main charging module is completed, the cells of the battery pack of the battery module are charged in sequence by the balance charger of the balance charging module.

Abstract: A card printer is disclosed which uses shaped-illumination to illuminate the portion of a card upon which printing will occur. The shaped-illumination is produced by passing light from a light source through a light source shaping assembly. In an embodiment, the light source shaping assembly is composed of a plurality of baffles molded into the portion of the printer which defines the path of motion of the printer's print head. In this way, alignment between the shaped-illumination and the printing process is guaranteed with essentially no increase in the cost of printer and, in many cases, a reduction in cost.

Abstract: Systems for reducing the power consumption of fluorescent lights are provided. The systems can be used in new construction as well as retrofitted into existing buildings employing overdriven fluorescent lights without significantly affecting the operation of utility power lines. In preferred embodiments, the systems provide substantially constant light output during start-up and low voltage conditions.

Abstract: Systems for reducing the power consumption of fluorescent lights are provided. The systems can be used in new construction as well as retrofitted into existing buildings employing overdriven fluorescent lights without significantly affecting the operation of utility power lines. In preferred embodiments, the systems provide substantially constant light output during start-up and low voltage conditions.

Abstract: A note stacker mechanism having a rotary motor with a shaft, a crank arm mounted onto the motor shaft, and a telescoping drive mechanism actuated by the crank arm for pushing a bank note into a storage box. Simplicity of design results in a low cost, compact stacker mechanism.

Abstract: A unitary guide and shield member (13) for use in guiding time cards (10) to a time and attendance recorder is provided. The guide and shield member serves to (1) guide the time card to feed rolls (16), (2) hold the time card at a substantially constant distance from a light source and a light sensor, and (3) protect the light sensor from ambient light.

Abstract: A body armor system having improved impact energy absorbing characteristics includes a projectile penetrant inhibiting layer and an impact energy absorbing layer positioned in overlying relation to one side of the projectile penetrant inhibiting layer such that the impact energy absorbing layer is adapted to absorb the impact energy from an incoming projectile. The impact energy absorbing layer spreads at least a portion of the impact energy in the plane of the impact energy absorbing layer. An anti-spalling layer is positioned on the opposite side of the projectile impact inhibiting layer. In another aspect of the invention, the impact energy absorbing layer contains a foam to further enhance impact energy absorption. Additionally, a temperature stabilizing means such as a phase change material is placed within the impact energy absorbing layer and provides thermal regulation.

Abstract: A computer bus includes a first original signal line, a second redundant signal line, circuitry connected to the first original signal line and the second redundant signal line for driving the first original signal line and the second redundant signal line so as to convey on each identical information, circuitry for receiving signals on the first original signal line and the second redundant signal line, and error checking circuitry for comparing the signals on the first original signal line and the second redundant signal line and for indicating an error if the signals differ. By providing redundant signals for each signal that cannot be check with parity (for example wired-OR signals), the potential for single undetected points of failure is eliminated. In accordance with another embodiment of the invention, a computer having multiple modules connected by a backplane bus.

Abstract: A user-initiated diagnostic test of a computer system is performed using a hardware abstraction layer including a diagnostic subsystem file and a diagnostic definition file, and also using diagnostic control routines and diagnostic status response routines. A selection is accepted from a user of a diagnostic subsystem to be tested from among a list of diagnostic subsystems stored in the diagnostic subsystem file. In accordance with information stored in the diagnostic definition file, the user is prompted for parameters of the selected diagnostic test, which are accepted from a user. These parameters are passed to the diagnostic control routine, which in response starts the selected diagnostic test. Diagnostic status response information from the diagnostic status response routine is received in the diagnostic control routine. The diagnostic status response information is presented to the user through a hardware-independent mechanism.

Abstract: A computer having multiple modules connected by a backplane bus includes multiple competition signal lines and multiple class signal lines. Access to the backplane bus to engage in one or more of multiple types of bus transactions is arbitrated between the modules by classifying the bus transactions into different classes and, during each of a succession of competition cycles, when a module wants access to the backplane bus to engage in a particular type of bus transaction, asserting a class signal line corresponding to a class in which the particular type of bus transaction has been classified. Based on information presented on the class signal lines, it is determined which modules are or are not eligible to compete for access to the backplane bus. When a module is eligible to compete for access to the backplane bus, it drives an identification code associated with the module on the competition signal lines.

Abstract: A cache coherency test exercises cache coherency logic exhaustively such that any cache coherency failures liable to occur will occur. The CPU(s) which caused the failure is automatically identified by performing an automatic CPU sort. In particular, cache coherency is tested by causing each processor in the system to perform a sequence of read and write accesses to main memory and to its own cache memory so as to cause substantially every possible sequence of cache coherency bus operations. Each processor tests consistency of data read by it with data written by it. As long as no processor detects an error, read and write accesses are continued for a predetermined period of time. When any processor detects an error, each CPU is disabled, one at a time, to see if the remaining CPUs can run the test successfully. If they do not, then every combination of two CPUs are disabled, then every combination of three, etc. In this manner, a maximum running set of CPUs is identified.

Abstract: A card rack includes parallel pairs of coplanar fins that extend inwardly from side walls whose spacing is adjustable. The inner edges of the coplanar fins are spaced apart so as to provide a passage for an elongated stop member that extends through all the compartments. Holes in tabs at both ends of the stop member receive self-tapping screws. The threaded portions of the screws engage opposed faces of upper and lower pairs of fins to secure the stop member in place. The screws can be loosened to slide the stop member along the upper and lower compartments and thereby adjust the depth of all the compartments.