Abstract: A manufacturing process and a power junction field-effect transistor (JFET) are provided. The basic concept of the present invention is to allow the current to flow vertically from the drain region on the bottom side to the source region on the topside of the device. By regulating the voltage applied between the gate regions and the source region, the power junction field-effect transistor (JFET) of the present invention can be built to handle large current and higher voltage for power management purposes, as is similar to the metal oxide semiconductor field effect transistor (MOSFET).
Abstract: A new low forward voltage drop Schottky barrier diode and its manufacturing method are provided. The method includes steps of providing a substrate, forming plural trenches on the substrate, and forming a metal layer on the substrate having plural trenches thereon to form a barrier metal layer between the substrate and the surface metal layer for forming the Schottky barrier diode.
Type:
Grant
Filed:
December 31, 2002
Date of Patent:
July 26, 2005
Assignees:
Pyramis Corporation, Delta Electronics, Inc.
Inventors:
Jun Zeng, Ming-Jiang Zhou, Tzong-Shiann Wu
Abstract: A method for manufacturing a gate pad protection structure applied in a power semiconductor device is provided. The method includes steps of (a) forming a gate oxide layer on a substrate, (b) forming a polysilicon layer on the gate oxide layer, (c) forming a polysilicon window and a polysilicon window array on the polysilicon layer, and (d) performing an ion implantation via the polysilicon window and the polysilicon window array.
Type:
Grant
Filed:
December 30, 2002
Date of Patent:
December 7, 2004
Assignee:
Pyramis Corporation
Inventors:
Jun Zeng, Ming-Jiang Zhou, Tzong-Shiann Wu