Patents Assigned to Q-Cells SE
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Patent number: 9548405Abstract: A solar cell includes a semiconductor layer, a collecting layer for collecting free charge carriers from the semiconductor layer and a buffer layer which is arranged between the semiconductor layer and the collecting layer. The buffer layer is designed as a tunnel contact between the semiconductor layer and the collecting layer. The buffer layer essentially includes a material with a surface charge density of at least 1012 cm?2, preferably of at least 5×1012 cm?2, and more preferably of at least 1013 cm?2.Type: GrantFiled: December 16, 2009Date of Patent: January 17, 2017Assignee: Q-CELLS SEInventors: Peter Engelhart, Sven Wanka, Wilhelmus Mathijs Marie Kessels, Gijs Dingemans
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Patent number: 9029690Abstract: A semiconductor device, in particular a solar cell, comprises a semiconductor substrate having a semiconductor substrate surface and a passivation composed of at least one passivation layer which surface-passivates the semiconductor substrate surface, wherein the passivation layer comprises a compound composed of aluminum oxide, aluminum nitride or aluminum oxynitride and at least one further element.Type: GrantFiled: May 31, 2011Date of Patent: May 12, 2015Assignee: Q-Cells SEInventors: Peter Engelhart, Robert Seguin, Wilhelmus Mathijs Marie Kessels, Gijs Dingemans
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Patent number: 8933525Abstract: The invention relates to a semiconductor apparatus and a method of fabrication for a semiconductor apparatus, whereby the semiconductor apparatus includes a semiconductor layer and a passivation layer arranged on a surface of the semiconductor layer and serving for passivating the semiconductor layer surface, whereby the passivation layer comprises a chemically passivating passivation sublayer and a field-effect-passivating passivation sublayer, which are arranged one above the other on the semiconductor layer surface.Type: GrantFiled: May 31, 2010Date of Patent: January 13, 2015Assignee: Q-Cells SEInventors: Peter Engelhart, Robert Seguin, Wilhelmus Mathijs Marie Kessels, Gijs Dingemans
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Patent number: 8679361Abstract: The invention relates to a method and device for characterizing wafers during the production of solar cells. Characterizing wafers includes a) providing a wafer and carrying out a production process with the wafer for producing a solar cell or a plurality of solar cells; b) carrying out a wet chemical step with the wafer during the production process, wherein the wet chemical step decreases an influence of the wafer surface on a lifetime of charge carriers in the wafer; c) irradiating the wafer with light for creating the charge carriers in the wafer during the wet chemical step or after the wet chemical step; d) determining the lifetime of the charge carriers created in step c); and e) characterizing the wafer by means of the lifetime determined in step d).Type: GrantFiled: October 11, 2007Date of Patent: March 25, 2014Assignee: Q-Cells SEInventors: Jörg Müller, Jörg Isenberg, Jörn Suthues, Martin Bivour, Jean Patrice Rakotoniaina
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Publication number: 20130003248Abstract: A method for picking up a substrate includes leading an electrostatic holder to the substrate, applying an electrical voltage having a first voltage value to the electrostatic holder in such a way that the substrate is accelerated in the direction of the electrostatic holder, and reducing the voltage applied to the electrostatic holder to a second voltage value, the absolute value of which is lower than the first voltage value.Type: ApplicationFiled: May 10, 2012Publication date: January 3, 2013Applicant: Q-CELLS SEInventors: Frank WEGERT, Torsten HÄNßGEN
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Publication number: 20120318351Abstract: A solar cell includes a substrate, a semiconductor layer, a first busbar, and a second busbar. Along a connecting line, the first busbar has contact pads which have a maximum width bImax, perpendicular to the connecting line and between which there is respectively located on the connecting line a current collecting area which makes contact with the contact pads in a contact area, having on both sides of the connecting line two outer points whose spacing perpendicular to the connecting line defines a maximum width bSmax of the current collecting area. Width b of the current collecting area and bImax<bSmax, starting from one contact pad up to an adjacent contact pad, decreases down to a minimum width bSmin between two inner points, and then increases up to the adjacent contact pad to a maximum width bSmax?.Type: ApplicationFiled: January 18, 2011Publication date: December 20, 2012Applicant: Q-CELLS SEInventors: Andreas Pfennig, Björn Faulwetter-Quandt, Andreas Hubert
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Publication number: 20120318347Abstract: An antireflection coating for a solar cell includes at least a first SiNx layer with a high refractive index and a second SiNx layer with a lower refractive index. An improved light coupling and a better passivation of solar cells and a more homogeneous and darker color impression may be achieved also in the laminated in solar module, while at the same time being insensitive to typical process variations.Type: ApplicationFiled: May 26, 2010Publication date: December 20, 2012Applicant: Q-CELLS SEInventors: Matthias Junghänel, Martin Schädel
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Publication number: 20120266947Abstract: The invention relates to a solar cell that comprises a planar semiconductor substrate with a front and a back; a multitude of holes that interconnect the front and the back; and current-collecting electrical contacts that are exclusively arranged on the back. The front comprises highly doped regions and lightly doped regions of a first type such that in each case the holes are situated in a highly doped region or adjoin such a region. According to a first aspect of the invention, the highly doped regions are arranged locally around the holes. According to a second aspect of the invention, the front comprises at least one region without holes, and the highly doped regions comprise one region or several regions that extends/extend to the at least one hole-free region. The invention furthermore relates to methods for manufacturing such solar cells.Type: ApplicationFiled: December 7, 2007Publication date: October 25, 2012Applicant: Q-CELLS SEInventors: Joerg Mueller, Robert Wade, Markus Hlusiak
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Publication number: 20120204930Abstract: A thin-layer solar module includes a plurality of interconnected solar cells, having in the order indicated the layers (a) a substrate 3; (b) a first electrode layer 4; (c) a semiconductor layer 5; and (d) a second electrode layer 6. At least one non-linear recess is disposed in the first electrode layer and a second non-linear recess is disposed in the second electrode layer and in the semiconductor layer, wherein a first projection of the first non-linear recess onto the substrate 3 and a second projection 10 of the second non-linear recess onto the substrate intersect or contact each other at least two projection points. The thin-layer solar module has at least one island-shaped contact region extending in a direction vertical to the substrate through the layers (a) through (d). A third recess is present in the semiconductor layer 5 within the island-shaped contact region 11 and is filled with an electrically conductive material.Type: ApplicationFiled: July 20, 2010Publication date: August 16, 2012Applicant: Q-CELLS SEInventor: Victor Verdugo
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Publication number: 20120167980Abstract: The invention relates to a solar cell with a semiconductor wafer comprising a light incidence facing front side with a base electrode, which is connected to a base layer of the semiconductor wafer, and a front side opposite to the back side with an emitter electrode, which is connected to an emitter structure of the semiconductor wafer, characterized by that the emitter structure comprises a front side emitter layer arranged on the front side of the semiconductor wafer.Type: ApplicationFiled: June 25, 2010Publication date: July 5, 2012Applicant: Q-CELLS SEInventor: Peter Engelhart
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Publication number: 20120111402Abstract: A solar cell includes a semiconductor substrate, a rear side passivation layer arranged on a light-remote rear side surface of the substrate, a covering layer arranged on the rear side passivation layer, and a metallization layer arranged on the covering layer. The covering layer has a protective layer section facing the rear side passivation layer and a contact layer section facing the metallization layers.Type: ApplicationFiled: November 4, 2011Publication date: May 10, 2012Applicant: Q-CELLS SEInventors: Matthias HOFMANN, Andrey STEKOLNIKOV, Robert SEGUIN, Maximilian SCHERFF, Andreas MOHR
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Publication number: 20120091566Abstract: The invention relates to a semiconductor apparatus and a method of fabrication for a semiconductor apparatus, whereby the semiconductor apparatus includes a semiconductor layer and a passivation layer arranged on a surface of the semiconductor layer and serving for passivating the semiconductor layer surface, whereby the passivation layer comprises a chemically passivating passivation sublayer and a field-effect-passivating passivation sublayer, which are arranged one above the other on the semiconductor layer surface.Type: ApplicationFiled: May 31, 2010Publication date: April 19, 2012Applicant: Q-CELLS SEInventors: Peter Engelhart, Robert Seguin, Wilhelmus Mathijs Marie Kessels, Gijs Dingemans
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Publication number: 20120042941Abstract: A back-side contact solar cell has a semiconductor layer (1) having a semiconductor surface (15) and a semiconductor area (3) adjoining the semiconductor surface (15) in the semiconductor layer (1) An electrode (23) is electrically connected to the semiconductor area (3), wherein the semiconductor area (3) forms a contact area (31) with the electrode (23) along the semiconductor surface (15) A passivation layer (7) is disposed on the semiconductor surface (15) for passivating the semiconductor surface by means of field effect passivation, wherein the passivation layer (7) extends substantially over the entire semiconductor surface (15), and a polarized or neutral buffer layer (9) is disposed between the semiconductor layer (1) and the passivation layer and encompasses the contact area (31).Type: ApplicationFiled: January 27, 2010Publication date: February 23, 2012Applicant: Q-CELLS SEInventors: Robert Seguin, Sven Wanka
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Publication number: 20120042925Abstract: A solar cell string contains a solar cell (1), formed by a wafer substrate (10) having a flat electrode contact segment (11), having a further solar cell (2) disposed adjacent to the solar cell (1), formed by a further wafer substrate (20) having a further flat electrode contact segment (21) and at least one cell connector (3) having a cell connector width and a cell connector thickness (3d) oriented substantially perpendicular to the electrode contact segments (11, 21). The cell connector extends along an extension direction (E) from the electrode contact segment (11) of the solar cell (1) to the further electrode contact segment (21) of the further solar cell (2), wherein the cell connector (3) electrically connects electrodes of the solar cell (1) to further electrodes of the further solar cell (2).Type: ApplicationFiled: January 11, 2010Publication date: February 23, 2012Applicant: Q-CELLS SEInventor: Andreas Pfennig
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Publication number: 20120032310Abstract: A process for producing a semiconductor device comprises the following process steps: provision of a semiconductor substrate (1); formation of a functional layer (2) on a semiconductor surface (11) of the semiconductor substrate (1); and production of at least one doped section (3) on the semiconductor surface (11) by driving a dopant into the semiconductor substrate (1) from the functional layer (2). The functional layer (2) is formed in such a way that it passivates the semiconductor surface (11), acting as a passivation layer upon completion of the semiconductor device.Type: ApplicationFiled: August 5, 2011Publication date: February 9, 2012Applicant: Q-CELLS SEInventors: Peter ENGELHART, Stefan BORDIHN, Maximilian SCHERFF, Bernhard KLÖTER
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Publication number: 20110308602Abstract: A solar cell includes a semiconductor substrate and an antireflection layer arranged on the light incidence side on the front-side surface of a semiconductor substrate. The antireflection layer has a limit voltage of less than 10 volts, less than 5 volts, or less than 3 volts, along a layer thickness of the antireflection layer.Type: ApplicationFiled: June 16, 2011Publication date: December 22, 2011Applicant: Q-CELLS SEInventors: Matthias JUNGHÄNEL, Andreas KUX, Martin SCHÄDEL, Maximilian SCHERFF
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Publication number: 20110308581Abstract: A solar cell includes a semiconductor layer, a collecting layer for collecting free charge carriers from the semiconductor layer and a buffer layer which is arranged between the semiconductor layer and the collecting layer. The buffer layer is designed as a tunnel contact between the semiconductor layer and the collecting layer. The buffer layer essentially includes a material with a surface charge density of at least 1012 cm?2, preferably of at least 5×1012 cm?2, and more preferably of at least 1013 cm?2.Type: ApplicationFiled: December 16, 2009Publication date: December 22, 2011Applicant: Q-CELLS SEInventors: Peter Engelhart, Sven Wanka, Wilhelmus Mathijs Marie Kessels, Gijs Dingemans
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Publication number: 20110290318Abstract: A semiconductor device, in particular a solar cell, comprises a semiconductor substrate having a semiconductor substrate surface and a passivation composed of at least one passivation layer which surface-passivates the semiconductor substrate surface, wherein the passivation layer comprises a compound composed of aluminium oxide, aluminium nitride or aluminium oxynitride and at least one further element.Type: ApplicationFiled: May 31, 2011Publication date: December 1, 2011Applicant: Q-CELLS SEInventors: Peter ENGELHART, Robert SEGUIN, Wilhelmus Mathijs Marie KESSELS, Gijs DINGEMANS
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Publication number: 20110284064Abstract: A solar cell includes a semiconductor layer with first doping, an inducing layer arranged on the semiconductor layer and an inversion layer or accumulation layer which due to the inducing layer is induced underneath the inducing layer in the semiconductor layer. The inducing layer includes a material with a surface charge density of at least 1012 cm?2, preferably of at least 5×1012 cm?2, more preferably of at least 1013 cm?2.Type: ApplicationFiled: December 16, 2009Publication date: November 24, 2011Applicant: Q-CELLS SEInventors: Peter Engelhart, Sven Wanka, Wilhelmus Mathijs Marie Kessels, Gijs Dingemans
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Patent number: D664084Type: GrantFiled: May 9, 2011Date of Patent: July 24, 2012Assignee: Q-Cells SEInventors: Björn Faulwetter-Quandt, Sven Wanka