Abstract: A structure and method for implementing a precision inductive component within a high frequency integrated circuit is disclosed. The inductive component has a structure of multiple conductive layers dielectrically insulated from each other and located above an integrated circuit substrate. The inductive component comprises a spiral-like inductive layer made of a first conductive layer. Additionally, a number of additional ground planes, each patterned out of its own selected conductive layer to minimize an induced eddy current therein thus improving Q (quality factor) under high frequency operation, are employed with either a linear or a rotational offset amongst them to effect a corresponding amount of adjustment of an inductance value of the inductive component. A number of specific design cases are presented with their respective inductance and RF performance parameters.

Abstract: A fundamental building block of 2-level series-gated CML-based CMOS circuit which includes a number of inductive components for an electronic circuit system is disclosed that is capable of driving a significant level of external capacitive load at a high input clock frequency while providing a high level of output signal fidelity for optical data communication. The inductive components can be implemented as either separate inductors or as differentially coupled pairs forming a corresponding transformer element. The value of any particular inductive component is first selected to approximately resonate, at the desired output signal frequency, with its associated equivalent node capacitance but further adjusted to a final value that results in a minimum output waveform distortion for the particular application. Two exemplary cases of application, a Divide-by-2 counter and a Master Slave D-type Flip Flop are presented with associated time domain output waveforms.

Abstract: A method of designing an electronic circuit system with multiple Field Effect Transistors (FETs) made by a variety of nonstandard industrial processes is presented. With this method, the circuit parameters of the various components of the individual functional building blocks of the circuit system are systematically adjusted to minimize the many deteriorating effects resulting from system-level interactions among these functional building blocks. In one embodiment, the method is applied to a Silicon On Insulator (SOI) CMOS IC that is a Divide-by-16 divider where the functional building blocks are four Divide-by-2 dividers. The resulting drastic improvement of output signal ripple from each divider stage is graphically presented. In another embodiment, the method is applied to another SOI CMOS IC that is a Bang Bang Phase Detector where the functional building blocks are three Master Slave D-Type Flip Flops. The resulting drastic improvement of output signal ripple is also graphically presented.

Abstract: A method of designing an electronic circuit system with multiple CMOS transistors is presented. With this method, the circuit parameters of the various CMOS transistors as well as the passive electrical components of the individual functional building blocks of the circuit system are systematically adjusted to minimize the many deteriorating effects resulting from system-level interactions among these functional building blocks. In one embodiment, the method is applied to a CMOS IC (Integrated Circuit) that is a Divide-by-16 divider where the functional building blocks are four Divide-by-2 dividers. The high quality of the resulting output signals from each divider stage is graphically presented. In another embodiment, the method is applied to a CMOS IC that is a Bang Bang Phase Detector where the functional building blocks are three Master Slave D-Type Flip Flops. The high quality of the resulting output signal is also graphically presented.

Abstract: A method of designing an electronic circuit system with multiple Bipolar transistor is presented. With this method, the circuit parameters of the various components of the individual functional building blocks of the system are systematically adjusted to minimize the many deteriorating effects resulting from system-level interactions among these functional building blocks. In one embodiment, the method is applied to a Bipolar IC that is a Divide-by-16 divider where the functional building blocks are four Divide-by-2 dividers. The resulting improvement of output signal ripple from each divider stage is graphically presented. In another embodiment, the method is applied to another Bipolar IC that is a Bang Bang Phase Detector where the functional building blocks are three Master Slave D-Type Flip Flops. The resulting improvement of output signal ripple is also graphically presented.

Abstract: A method of designing a system of electronic circuit is presented. With this method the circuit parameters of the components of the individual functional building blocks of the system are systematically adjusted to minimize the deteriorating effect resulting from system-level interactions among these functional building blocks. In one embodiment, the method is applied to a CMOS IC that is a Divide-by-16 divider where the functional building blocks are four Dividing by-2 dividers. The resulting improvement of output signal ripple from each devided stage is graphically presented. In another embodyment, the method is applied to another CMOS IC that is a Bang Bang Phase Detector where the functional building blocks are three Master Slave D-Type Flip Flops. The resulting improvement of output signal ripple is also graphically presented.