Abstract: An integrated circuit substrate (100) including a conductive trace layer (102) formed by one or more conductive traces that are deposited on a partially or completely removable carrier (101), a stud conductive trace layer (103) formed by one or more stud traces that are disposed on at least one conductive trace of the conductive trace layer (102), in which each stacked conductive trace and stud trace forms an electronic conductive trace, and all electronic conductive traces positioned at the same level is defined as for forming an electronic conductive layer; a dielectric layer (104) occupying spaces within the stud conductive trace layer (103) and conductive trace layer (102), and at least one recess (105) formed at the electronic conductive trace of at least one electronic conductive layer, or between two electronic conductive traces of at least one electronic conductive layer, wherein each recess (105) exposes at least a portion of the conductive trace layer (102), stud conductive trace layer (103), dielec

Abstract: An integrated circuit packaging is described, including a plurality of electrical circuits developed using a first patterned conductive layer on a base, wherein an electrical circuit is formed by using a masking material, and an interconnection is developed between the electrical circuits, where the interconnection is disposed on at least one side of the first patterned conductive layer and masking material, in which the interconnection is enclosed with a second masking material to form the integrated circuit packaging.

Abstract: An integrated circuit substrate and its method of production are described. The integrated circuit substrate comprises at least an internal conductive trace layer formed by one or more internal conductive traces that is deposited on a partially or completely removable carrier; and a dielectric layer encapsulating the internal conductive trace layer through a lamination process or a printing process. The top surface of the topmost internal conductive trace layer and bottom surface of the bottommost internal conductive trace layer are exposed and not covered by the dielectric layer. External conductive trace layer can also be deposited outside of the dielectric layer. The internal conductive trace layers are deposited through plating or printing of an electronically conductive material, whereas the external conductive trace layer is deposited through electroless and electroplating, or printing of the electronically conductive layer.

Abstract: An integrated circuit package and manufacturing method thereof are described. The integrated circuit package includes pin up conductive plating to form an interconnect, where an opening on a patterned fifth layer photo-resist material located at bottom portion of a base developed for etching selectively the base to form at least an internal opening and at least a positioning opening, wherein the internal opening corresponds with an inside area of a first patterned conductive layer, and the positioning opening corresponds with an outside area of the first patterned conductive layer.

Abstract: A method of depositing one or more stiffener onto a wiring board includes the steps of engaging the wiring board onto a heat-retaining pallet to form an assembly, pre-heating the assembly to a temperature ranged from 70 to 140° C., and disposing the stiffeners onto the pre-heated wiring board of the assembly, wherein the pallet of the assembly retains sufficient heat for the wiring board to at least partially melt the stiffener, more preferably adhesive stiffener, to fix onto the wiring board upon disposition of the stiffeners.