Abstract: A common Delay Locked Loop (DLL) circuit and/or voltage generator circuit is provided in, or associated with. a memory interface interposed between a memory controller and a plurality of memory components. Corresponding circuits in the memory components are disabled and/or bypassed, or the memory components are manufactured without the circuits. Both the DLL circuit and voltage generator draw current, which is multiplied by the number of memory components in a memory system. By operating a single DLL circuit and/or voltage generator in or associated with the memory interface, that generates a read clock signal and/or various voltage levels, respectively, for all memory components in the memory system, power consumption may be significantly reduced.

Abstract: In one embodiment, a memory device comprises a plurality of memory banks. At least two of the memory banks share the same bus. Logic is coupled to the memory banks via the different buses. The logic controls access to the memory banks. A bi-directional tri-state buffer is interposed between adjacent memory banks along the same bus so that each bus is segmented into a plurality of sections, each bus section being coupled to one or more different ones of the memory banks.

Abstract: In one embodiment, an integrated circuit comprises circuitry for performing bus inversion. The circuitry is operable to configure the integrated circuit to implement one of a plurality of bus inversion schemes each of which the integrated circuit is capable of performing. The circuitry is also operable to process data input to and output from the integrated circuit based on the bus inversion scheme for which the integrated circuit is configured.

Abstract: In one embodiment, a memory device comprises a semiconductor substrate, a first set of memory banks disposed on the semiconductor substrate and a second set of memory banks disposed on the semiconductor substrate. Each memory bank of the second set is split into a plurality of memory bank segments physically separated from each other and from the first set of memory banks. Each memory bank segment is arranged adjacent to, and occupies less area than, one of the memory banks of the first set.

Abstract: According to the embodiments described herein, an enable signal generator has two stages. Each stage offsets transistor performance variation in the other stage to produce an enable signal output relatively immune from the effects associated with transistor mismatches. In one embodiment, a memory device comprises a plurality of memory cells, sense amplifier circuitry and the enable signal generator. The sense amplifier circuitry is coupled to one or more of the memory cells and senses the state of the one or more memory cells when enabled. The enable signal generator has first and second stages and generates an enable signal applied to the sense amplifier circuitry. The enable signal generator counteracts delay variation when generating the enable signal so that operation of the enable signal generator is substantially unaffected by transistor performance variation in either stage of the enable signal generator.

Abstract: The present invention, in one embodiment, provides a method of producing a PN junction the method including providing a single crystal substrate; forming an insulating layer on the single crystal substrate; forming a via through the insulating layer to provide an exposed portion of the single crystal substrate; forming amorphous Si on at least the exposed portion of the single crystal substrate; converting at least a portion of the amorphous Si into single crystal Si; and forming dopant regions in the single crystal Si. In one embodiment the diode of the present invention is integrated with a memory device.

Abstract: An integrated circuit includes one or more memory array segments configured to store information and a refresh controller. Each memory array segment has a plurality of memory cells arranged in rows selectable through a row address. The refresh controller is configured to monitor row address activity to identify which bits of the row address change state at least once during a memory access operation and to skip refresh of the rows associated with the row address bits that do not change state at least once during the memory access operation.

Abstract: A memory device comprises sense amplifier circuitry, a current sink and a resistive element. The sense amplifier circuitry is operable to evaluate data read from a memory array included in the memory device responsive to a bias voltage applied to the sense amplifier circuitry. The current sink is operable to sink a bias current. The resistive element couples the current sink to the sense amplifier circuitry. The bias voltage applied to the sense amplifier circuitry corresponds to the voltage drop across the resistive element and current sink as induced by the bias current.

Abstract: A memory device and a method of reading the same includes a phase change element having a data state associated therewith that features maintaining the consistency of the data state of the phase change element in the presence of a read current. The memory circuit includes a sense amplifier that defines a sensing node. Circuitry selectively places the bit line in data communication with the sensing node, defining a selected bit line. A current source produces a read current, and a switch selectively applies the read current to the sensing node. Logic is in electrical communication with the sensing node to control the total energy to which the phase change material is subjected in the presence of the read current so that the data state remains consistent.