Abstract: A memory cell includes a first electrode having a first region and a second region, a second electrode and a phase change material. The phase change material is interposed between the first electrode and the second electrode with the first region of the first electrode arranged closer to the phase change material than the second region. The first region of the first electrode includes an inner portion laterally surrounded by an outer portion. The outer portion has a greater resistivity than the inner portion. The second region of the first electrode has the same resistivity as the inner portion of the first region.

Abstract: A temperature control circuit, comprising: a plurality of temperature sensors each configured to measure a temperature of a corresponding memory chip chosen from a plurality of memory chips, and to generate a sensor output signal that is set to a first voltage if the measured temperature of the corresponding memory chip meets a temperature requirement, and is set to a floating voltage if the measured temperature of the corresponding memory chip does not meet the temperature requirement, the sensor output signal being connected to an intermediate node; a current source connected to the intermediate node; and a control circuit configured to provide chip control signals to the plurality of memory chips.

Abstract: Multiplexer control logic is provided for a semiconductor memory device that combines the function of programmable disconnect-state with a dynamic or dynamic latching mode that operates during self-refresh. The programmable disconnect state disconnects the sense amplifier from a memory array segment when it is unselected. When a memory array segment is being accessed, (such as during self-refresh), the multiplexers are latched into a selected state thereby eliminating the multiplexer switching current while the memory array segment is being accessed.