Abstract: Methods and systems for network communication are provided. A method includes maintaining a first segment of a routing data structure at a first switching module of a network adapter for routing a frame between virtual machines executed by a computing device operationally coupled to the network adapter; maintaining a second segment of the routing data structure at a second switching module for routing a frame received at a port of the network adapter to an external destination; receiving a frame from the computing device and using the first segment by the first switching module to route the frame to a destination virtual machine; and receiving a frame at a port of the network adapter and using the second segment of the routing structure by the second switching module to the route the frame to its destination without providing the frame to the computing device.

Abstract: Methods and systems for network communication are provided. One method includes, receiving a network packet at a first network interface card (NIC) operationally coupled to a computing device; identifying a second NIC as a destination for the network packet; placing the network packet by the first NIC at a host memory location, without utilizing resources of a processor of the computing device; notifying the second NIC that the network packet has been placed at the host memory location; retrieving the network packet by the second NIC from the host memory location; transmitting the network packet by the second NIC to another destination; notifying the first NIC by the second NIC that the packet has been transmitted by the second NIC; and freeing the host memory location by the first NIC.

Abstract: Methods and systems for a device coupled to a computing device are provided. As an example, one method includes receiving a request for processing an address list control block (ALCB) by an ALCB offload engine of an adapter coupled to a computing device; determining by the ALCB offload engine if the ALCB is located at a cache managed by a cache controller of the ALCB engine; forwarding the ALCB to an address computation module that determines an address of a memory location of the computing device, where the ALCB stores the address of the memory location in an address list; generating a direct memory access (DMA) request to retrieve the ALCB from an adapter memory, when the ALCB is not located at the cache; and storing the ALCB at the cache, after the ALCB is received in response to the DMA request.

Abstract: Methods and systems for routing control blocks is provided. One method includes receiving a control block from a computing device at an adapter having a plurality of hardware engines for processing control blocks, where the control blocks are to read data, write data, obtain status for an input/output request and perform a management task; evaluating the control block by the adapter to determine that the control block is a continuation control block for data transfer using more than one control block; is a direct route control block for a specific hardware engine; or is for a management task; routing the control block to a same hardware engine when the control block is a continuation control block; and routing the control block to a master hardware engine from among the plurality of hardware engines, when the control block is for the management task.

Abstract: Methods and systems for network communication are provided. One of the methods includes receiving an out of order packet at a requestor device that is communicably connected to a responder device; storing the out of order packet at an out of order buffer location; and sending a lossy reliable connection (LRC) packet to the responder device when selective acknowledgement (SACK) is supported between the requestor device and the responder device, with information regarding an updated sequence number in a LRC extended header (LRCETH) that indicates to the responder information regarding in-order packets that have been received by the requestor device.

Abstract: Methods and systems for optimizing data structures to efficiently control network data transfers are provided. For example, the method includes determining common key type sets from a plurality of network processing rules; creating one or more hash data structures using the most common key type sets; programming network processing rules that use the most common key type sets into the one or more hash data structures; programming remaining network processing rules into a content addressable memory (CAM); and using the one or more hash data structures and the CAM to find an appropriate network processing rule to process a network packet.

Abstract: Methods and systems for network devices is provided. In one aspect, a network device includes a plurality of ports, where the plurality of ports are configured to operate in a first operating mode as a single port at a first speed and in a second operating mode where each of the plurality of ports operate as an independent port at a second operating speed; a shared memory device for staging information received from a network for the plurality of ports operating in the first operating mode and the second operating mode; a receive port selector that selects information from the shared memory device when the plurality of ports are operating in the second operating mode; and a shared error correction code module for decoding and performing error correction on information received via the network for the first operating mode and the second operating mode.

Abstract: A network device is provided. The network device includes a port complex having a plurality of ports configured to operate at different operating speeds for sending and receiving information complying with different protocols. The network device further includes a processor complex having a plurality of processors for processing information complying with different protocols and received by the plurality of ports; and a message queuing system (MQS) for managing messages for the plurality of processors regarding the received information complying with different protocols. Each processor can process information complying with any of the different protocols.

Abstract: Methods and systems for routing frames are provided. A system includes an initiator operationally coupled to a first switch that is coupled to a second switch. The first switch includes a plurality of ports for sending and receiving frames and includes a routing table that identifies a port identifier steering table based on an area field of a frame header of a frame received by the first switch. The first switch also includes a plurality of port identifier tables, where each port identifier table is associated with a unique area field and identifies a same port of the first switch for a plurality of area fields. The second switch stores an area steering table with port identification information associated with an area field of a frame header of a frame received by the second switch and a same port of the second switch is assigned to multiple area fields.

Abstract: In some embodiments, the execution of load and store instructions for internal fields of data structures is accelerated by using on-chip template registers and appropriate machine code instructions. A load/store machine code instruction comprises an identifier of a memory address offset of an internal field word relative to a base address of the data structure, an identifier of an intra-word start bit of the internal field, and an identifier of an intra-word length of the internal field. The three identifiers may coincide, for example if the three identifiers are represented by an identity of a template register storing a template entry including the memory address offset, the start position, and the field length. The three identifiers may also be provided as part of a machine code instruction itself. Further provided are compilers, compiler methods, and hardware systems for implementing accelerated internal-field load and store operations.

Abstract: In some embodiments, a system allowing a flexible upgrade of a computer system (e.g. server) to a high-speed network connection comprises base configuration motherboard or network card including a set of low-speed (e.g. 1 Gbps Ethernet) media access controllers (MACs) each connected to a low-speed physical controller (PHY), and a set of high-speed (e.g. 10 Gbps Ethernet) MACs. An expansion card including high-speed PHYs of choice can be connected by an end user to the base configuration motherboard or network card. A flow classifier classifies data sent/received over both high-speed and low-speed ports, and a single driver may control both high- and low-speed ports. One or both of the motherboard and/or expansion card are configured according to a detected type (e.g. physical layer standard, vendor) of expansion card connected to the motherboard and/or type of physical medium connected to the expansion card.

Abstract: In some embodiments, a hardware linked-list manager includes a wildcard search controller for generating corresponding queue-specific read requests from wildcard read requests. The linked-list manager may be part of an on-chip interagent switch for allowing a plurality of agents to communicate with each other. The interagent switch may include a crossbar switch and a plurality of hardware linked-list managers integrated on the chip, connected to a random access memory, and connected to the crossbar switch such that the crossbar switch is capable of connecting each of the linked-list managers to each of the agents. Each linked-list manager sends agent-generated data to the memory for storage in the memory as a linked-list element, and retrieves linked-list elements from memory in response to agent read requests. A shared free-memory linked-list manager may maintain a linked list of free memory locations, and provide free memory address locations to a linked list manager upon request.

Abstract: A dual-mode network storage controller integrated on a chip is connected to a first set of hosts over a block-level storage area network (SAN), and to a second set of hosts over a metadata Ethernet/IP network. The dual-mode storage controller is also connected to one or more storage devices, such as a Redundant Array of Independent Disks (RAID). The storage controller comprises dedicated-hardware metadata translation logic for translating metadata (e.g. file-level) storage commands into block-level storage commands. The storage controller can also include block translation logic for translating logical block-level storage commands into physical block-level storage commands. The storage controller further comprises multiplexing logic for sequentially transmitting to the storage device(s) block level storage commands derived from the commands received from the first set of hosts and the second set of hosts.

Abstract: A method for routing fibre channel frames using a fibre channel switch element is provided. The switch element includes, a receiving segment in a fibre channel port for receiving the frames and a transmit segment that transmits the received frames. The method includes requesting an early frame transfer, wherein the transmit segment of a fibre channel port requests an early frame transfer from a receiving segment of the fibre channel port before a frame has arrived at the transmit segment; activating an early frame transfer; determining if there is a need for aborting the early frame transfer request; and selecting a different source port if there is a need for aborting an early frame transfer request.

Abstract: Method and system for routing Fibre Channel Class F frames using a Fibre Channel switch element port is provided. The method includes parsing a Fibre Channel frame at a receive port of a Fibre Channel switch; and automatically routing a Class F frame that is destined to a Domain Controller. The switch element includes a receive port for parsing a Fibre Channel frame, storing a Domain Steering Table and automatically routing a Class F frame that is destined for a Domain Controller.

Abstract: A fibre channel switch element with an acceleration device that connects plural fibre channel devices in an arbitrated loop and monitors frames sent during a loop initialization process is provided. The acceleration device creates an AL_PA table selected by each fibre channel device, wherein the AL_PA table is used for port selection; and during an arbitration process sends a benign primitive to non-arbitrating devices. The acceleration device includes, a global arbitration module, a state machine module, and a matrix for connecting plural fibre channel devices.

Abstract: Method and system for arbitrating between plural arbitration requests is provided. The system includes a plurality of first stage arbiters that receive plural arbitration requests and a signal that indicates a previously granted request, wherein the first stage arbiters assert a high priority request signal if a high priority request is pending and a low priority request signal is asserted, if a low priority request is pending; a second stage arbiter that arbitrates between high priority requests, when high priority requests are pending; wherein if a high priority request is not pending, then a low priority request is granted; and a data handler module that operates in parallel with the second stage arbiter to immediately move data associated with a request that is granted at any given time.

Abstract: A router for use in a network includes a scalable architecture and performs methods for implementing quality of service on a logical unit behind a network port; and for implementing storage virtualization. The architecture includes a managing processor, a supervising processor; and a plurality of routing processors coupled to a fabric. The managing processor has an in-band link to a routing processor. A routing processor receives a frame from the network, determines by parsing the frame, the protocol and logical unit number, and routes the frame to a queue according to a traffic class associated with the logical unit number in routing information prepared for the processors. An arbitration scheme empties the queue in accordance with a deficit round robin technique. If a routing processor detects the frame's destination is a virtual entity, and so is part of a virtual transaction, the router conducts a nonvirtual transaction in concert with the virtual transaction.

Abstract: A gasket retainer is mounted on a connector body to hold a rounded conductive gasket in position around an open end of the connector body. The gasket retainer has an elongated body with an upper surface, a lower surface and a central open portion to form an outer peripheral portion, surrounding the central open portion, having two side edges and two end walls. Gasket retaining portions, which may be a number of fingers extend upwardly away from the upper surface of the two side edges and recesses are formed in the two end walls to allow holding portions on the connector body to secure the retainer adjacent the open end with the rounded conductive gasket held in position, flush against the connector body to improve the shielding effectiveness in fibre channel SFP transceiver electro magnetic compatibility when connected.

Abstract: A method and system for monitoring frame flow in a Fiber Channel network is provided. The method includes, deleting fill words before any frame data is allowed to be stored in a buffer memory; storing only certain primitive signals and/or frame data in the buffer memory; reading the buffer memory without delay, if a primitive signal is stored in the buffer memory; and delaying reading the buffer memory if frame data is detected. The network includes, a host bus adapter that includes a fiber channel protocol manager that includes a receive logic that deletes fill words before any frame data is allowed to be stored in a buffer memory, wherein the buffer memory stores only certain primitive signals and/or frame data and the buffer memory is read without any delay, if a primitive signal is stored, while a read operation of the buffer memory involving frame data is delayed.