Abstract: Method for receiving data packet transmissions, wherein synchronization with a transmitter is accomplished based on detection of a preamble transmitted by the transmitter. A time multiplexing scheduling of a single hardware receiver arrangement is used, and the time multiplexing scheduling has a main time slot comprising a first listen period and a second listen period following the first listen period. In the first listen period a first type of synchronization detection is executed (e.g. IEEE 802.15.4), and in the second listen period a second type of synchronization detection different from the first type of synchronization detection is executed (e.g. BLE).

Abstract: Bias circuitry is disclosed with a bias drive device having a first current terminal coupled to a voltage supply node, a bias control terminal coupled to a control node, and a second current terminal coupled to a bias output node. An impedance control device has a third current terminal and an impedance control terminal that are coupled together and a fourth current terminal coupled to ground. An output impedance resistor is coupled between the third current terminal and the bias output node. A pull-down device is coupled between the bias output node and the fixed voltage node, wherein a higher voltage applied to the control node sets an output impedance at the bias output node to approximately a lower impedance of the pull-down device and a lower voltage applied to the control node sets the output impedance to approximately the resistance of the output impedance resistor.

Abstract: A transceiver device comprising transceiver circuitry (5) coupled to one or more antenna ports (2; 2?) by a balun arrangement (Lb, Lu; Lu?). For each of the antenna ports (2; 2?) an antenna switch (Ta; Ta?) is present having an antenna enabling input (4; 4?) and being arranged to connect an unbalanced coil (Lu; Lu?) from the balun arrangement (Lb, Lu; Lu?) to the antenna port (2; 2?) and a ground port (3). Also an electro-static discharge (ESD) protection circuit is provided with an ESD switch (Te; Te?) arranged to connect the antenna port (2; 2?) to the antenna enabling input (4; 4?) of the antenna switch (Ta; Ta?). The ESD switch (Te; Te?) has an ESD switch control input (A) connected to an ESD trigger arrangement (Rtrigger).

Abstract: Bias circuit and a bias generator circuit comprising such a bias circuit. The bias circuit (10, 11) comprises a switched capacitor resistor circuitry (C1, C2, M12-M17), and an operational amplifier (M1-M4, M10) with an input differential transistor pair (M1, M2). The bias circuit further comprises additional source follower transistors (M5, M6) associated with the first and second input differential transistors (M1, M2). The bias generator circuit has a PMOS switched capacitor reference circuit (11) and a NMOS switched capacitor reference circuit (10) and a transconductor reference cell (15). The transconductor reference cell (15) is a replica of a basic reference cell used in a further circuit.

Abstract: Balun circuit arrangement with a balanced port side having two balanced terminals and an unbalanced port side having an unbalanced terminal. A first series connection of a first inductive impedance element (L1) and a first capacitive impedance element (C1) is present between a negative terminal of the two balanced terminals and the unbalanced terminal. A second series connection of a second inductive impedance element (L2) and a third inductive impedance element (L3) is present between a positive terminal of the two balanced terminals and the unbalanced terminal, and a second capacitive element (C2) is connected between a node connecting the second and third inductive element and a ground connection. The balun circuit arrangement may be used in a combination with an oscillator circuit and a single ended antenna.

Abstract: Method and receiver for acquiring a data packet in a signal transmission like Bluetooth Low Energy (BLE), wherein the data packet comprises a preamble code (2) followed by an access code (3) and has a symbol period. The following steps are executed: —executing a preamble correlation (8) continuously on a received signal (10) using the preamble code (2); —determining a frequency estimate (14) and a timing estimate (13) from the preamble correlation (8); —using the frequency estimate (14) to execute a frequency correction (15) on the received signal; —performing an access code correlation (9) on the frequency corrected received signal, in parallel with the continuous execution of the preamble correlation (8); and —detecting a data packet (19) when the access code correlation (9) is higher than a predetermined access code threshold (18) at an expected time relative to the timing estimate (13).

Abstract: Balun circuitry with a transceiver loop, a first antenna loop, and a second antenna loop is disclosed. The first antenna loop, the second antenna loop, and the transceiver loop are coaxially positioned such that the first antenna loop and the second antenna loop are coupled in opposite phase to the transceiver loop. In at least one exemplary embodiment, a semiconductor substrate has a layer that includes the first antenna loop, the second antenna loop, and the transceiver loop.

Abstract: Multi-channel listening capable receiver capable of operating on one of K data channels and method of operating such a receiver. A local oscillator (2) is provided for tuning the receiver (1) to one of the channels within a channel switching time Ts, as well as a processing unit (9) arranged to detect a presence of a preamble on the tuned channel. The processing unit (9) is further arranged to switch over the local oscillator (2) to a next one of the data channels if no presence of a preamble is detected within a single preamble symbol duration Tp. The channel switching time is a fraction ? of a single preamble symbol period Tp. The number of data channels K fulfills the condition K<floor (N?1?(K*?)) to be able to receive all relevant data packets on the K channels, after being triggered by reception of the preamble.

Abstract: Balun circuit arrangement with a balanced port side having two balanced terminals and an unbalanced port side having an unbalanced terminal. A first series connection of a first inductive impedance element (L1) and a first capacitive impedance element (C1) is present between a negative terminal of the two balanced terminals and the unbalanced terminal. A second series connection of a second inductive impedance element (L2) and a third inductive impedance element (L3) is present between a positive terminal of the two balanced terminals and the unbalanced terminal, and a second capacitive element (C2) is connected between a node connecting the second and third inductive element and a ground connection. The balun circuit arrangement may be used in a combination with an oscillator circuit and a single ended antenna.

Abstract: Balun circuit which is configured in an on-chip design, and multi-port antenna switch circuit comprising such a balun circuit. The balun circuit has a transceiver loop (3), as well as a first antenna loop (1) and at least one further antenna loop (2). The first antenna loop (1), the at least one further antenna loop (2), and the transceiver loop (3) are coaxially positioned in one layer of the on-chip design. The multi-port antenna switch circuit further has a first switch (T1) connected between a ground terminal (A1GND) of the first antenna loop (1) and a first antenna external connection pad (Pg1), and a second switch (T2) connected between a ground terminal (A2GND) of the at least one further antenna loop (2) and at least one further antenna external connection pad (Pg2).

Abstract: Existing multi-band/multi-mode (MB/MM) power amplifiers (PAs) use separate signal paths for the different covered frequency bands. This results in a large degree of hardware duplication and to a large die size and cost. Solutions that achieve hardware sharing between the different signal paths of MB/MM PAs are shown. Such sharing includes bias circuit and bypass capacitors sharing, as well as sharing front-end stages and the output stage of the PA. Signal multiplexing may be realized in the transmitter or at the PA front-end while the signal de-multiplexing can be realized either in the PA output stage or at the front-end of the output stage. Such circuits can be applied with saturated and linear MB/MM PAs with adjacent or non-adjacent bands.

Abstract: Circuitry, which includes a package interface, a radio frequency (RF) amplification circuit, and a closed-loop gain linearization circuit. The package interface receives an RF signal and provides an amplified RF signal. The RF amplification circuit amplifies the RF signal in accordance with a gain of the RF amplification circuit so as to generate the amplified RF signal. In one embodiment, the closed-loop gain linearization circuit is configured to endogenously establish a target gain magnitude using the RF signal and linearize the gain of the RF amplification circuit in accordance with the target gain magnitude. By endogenously establishing the target gain magnitude using the RF signal, the closed-loop gain linearization circuit can provide linearity with greater independence from external control circuitry.