Abstract: A method of fabricating a MMIC system includes providing an engineered substrate including a growth substrate and a device layer coupled to the growth substrate, fabricating a plurality of MMIC device elements using the device layer, and providing a carrier substrate including a plurality of metallic structures. The method also includes bonding the plurality of metallic structures to the plurality of MMIC device elements, removing a portion of the growth substrate, and removing a portion of the carrier substrate. The method further includes forming a ground/power plane coupled to the growth substrate, forming a plurality of vias passing from the ground/power plane to one or more of the plurality of MMIC device elements, and joining a cooling structure to the carrier substrate.

Abstract: A monolithic microwave integrated circuit (MMIC) system includes a growth substrate, a device layer coupled to the growth substrate, a plurality of MMIC device elements coupled to the device layer, and a plurality of metallization structures coupled to the plurality of MMIC device elements. The MMIC system also includes a carrier substrate coupled to the plurality of metallization structures and a cooling structure coupled to the carrier substrate.

Abstract: An engineered substrate includes a polycrystalline ceramic core, a first adhesion layer coupled to the polycrystalline ceramic core, a conductive layer coupled to the first adhesion layer, a second adhesion layer coupled to the conductive layer, a diffusion barrier layer coupled to the second adhesion layer, and a bonding layer coupled to the diffusion barrier layer. The engineered substrate also includes a substantially single crystal layer coupled to the bonding layer. A first region of the engineered substrate includes an epitaxial III-V layer coupled to the substantially single crystal layer. A second region of the engineered substrate includes a eutectic barrier layer coupled to the bonding layer, a planarization layer coupled to the eutectic barrier layer, and an epitaxial III-V layer coupled to the planarization layer.

Abstract: An engineered substrate includes a polycrystalline ceramic core, a eutectic barrier layer coupled to the polycrystalline ceramic core, a first adhesion layer coupled to the eutectic barrier layer, a conductive layer coupled to the first adhesion layer, a second adhesion layer coupled to the conductive layer, and a diffusion barrier layer coupled to the second adhesion layer. The engineered substrate also includes a bonding layer coupled to the diffusion barrier layer, a substantially single crystal layer coupled to the bonding layer, and an epitaxial III-V layer coupled to the substantially single crystal layer.

Abstract: An engineered substrate includes a polycrystalline ceramic core having a device surface and a support surface opposite the device surface and a polycrystalline layer free of a binding agent coupled to the device surface. The polycrystalline grains can include aluminum nitride and the binding agent can include yttrium aluminum garnet. The polycrystalline layer can consist of aluminum nitride and be free of yttrium. An engineered substrate with a polycrystalline shell includes a polycrystalline ceramic core having a device surface, a support surface opposite the device surface, and peripheral surfaces extending between the device surface and the support surface. The engineered substrate with a polycrystalline shell also includes a polycrystalline shell free of a binding agent encapsulating the polycrystalline ceramic core.

Abstract: An engineered substrate structure includes a ceramic substrate having a front surface characterized by a plurality of voids, and a barrier layer encapsulating the ceramic substrate. The barrier layer defining a plurality of valleys corresponding to the plurality of voids. The engineered substrate structure further includes a first bonding layer comprising a bonding layer material and coupled to the barrier layer on the front surface of the ceramic substrate. The first bonding layer defines a plurality of fill regions filled with the bonding layer material in the plurality of valleys corresponding to the plurality of voids. The engineered substrate structure further includes a second bonding layer coupled to the first bonding layer, and a substantially single crystalline layer joined to the second bonding layer.

Abstract: A substrate includes a support structure comprising a polycrystalline ceramic core, a first adhesion layer encapsulating the polycrystalline ceramic core, a barrier layer encapsulating the first adhesion layer, a second adhesion layer coupled to the barrier layer, and a conductive layer coupled to the second adhesion layer. The substrate also includes a bonding layer coupled to the support structure, a substantially single crystal silicon layer coupled to the bonding layer, and an epitaxial semiconductor layer coupled to the substantially single crystal silicon layer.

Abstract: An engineered substrate structure includes a ceramic substrate having a front surface characterized by a plurality of peaks. The ceramic substrate includes a polycrystalline material. The engineered substrate structure also includes a planarization layer comprising a planarization layer material and coupled to the front surface of the ceramic substrate. The planarization layer defines fill regions filled with the planarization layer material between adjacent peaks of the plurality of peaks on the front surface of the ceramic substrate. The engineered substrate structure further includes a barrier shell encapsulating the ceramic substrate and the planarization layer, wherein the barrier shell has a front side and a back side, a bonding layer coupled to the front side of the barrier shell, a single crystal layer coupled to the bonding layer, and a conductive layer coupled to the back side of the barrier shell.

Abstract: An engineered substrate structure includes a ceramic substrate having a front surface characterized by a plurality of peaks. The ceramic substrate includes a polycrystalline material. The engineered substrate structure also includes a planarization layer comprising a planarization layer material and coupled to the front surface of the ceramic substrate. The planarization layer defines fill regions filled with the planarization layer material between adjacent peaks of the plurality of peaks on the front surface of the ceramic substrate. The engineered substrate structure further includes a barrier shell encapsulating the ceramic substrate and the planarization layer, wherein the barrier shell has a front side and a back side, a bonding layer coupled to the front side of the barrier shell, a single crystal layer coupled to the bonding layer, and a conductive layer coupled to the back side of the barrier shell.

Abstract: A substrate includes a support structure comprising a polycrystalline ceramic core, a first adhesion layer encapsulating the polycrystalline ceramic core, a barrier layer encapsulating the first adhesion layer, a second adhesion layer coupled to the barrier layer, and a conductive layer coupled to the second adhesion layer. The substrate also includes a bonding layer coupled to the support structure, a substantially single crystal silicon layer coupled to the bonding layer, and an epitaxial semiconductor layer coupled to the substantially single crystal silicon layer.

Abstract: A method of fabricating a semiconductor device includes providing an engineered substrate. The method further includes forming an epitaxial gallium nitride (GaN) layer coupled to the engineered substrate, forming a plurality of trenches in the epitaxial GaN layer, and forming a plurality of gates in the trenches. The method further includes forming a plurality of sources coupled to the epitaxial GaN layer, forming an interconnect structure on the gates and sources, forming a metal bonding layer on the interconnect structure, bonding a conductive carrier to the metal bonding layer, removing the engineered substrate, forming a drain layer on the back surface of the epitaxial GaN layer, etching at least one portion of the epitaxial GaN layer and the interconnect structure to form at least one gate pad recess and expose the embedded metal track; and forming at least one gate electrode in the gate pad recess.

Abstract: A substrate including a support structure. The support structure including a polycrystalline ceramic core and a first adhesion layer coupled to the polycrystalline ceramic core. The support structure further including a conductive layer coupled to the first adhesion layer, a second adhesion layer coupled to the conductive layer, and a barrier layer coupled to the second adhesion layer. The substrate further including a bonding layer coupled to the support structure. The substrate further including a substantially single crystal layer comprising at least one of silicon carbide, sapphire, or gallium nitride coupled to the bonding layer. The substrate further including an epitaxial semiconductor layer coupled to the substantially single crystal layer.

Abstract: A method of forming a doped gallium nitride (GaN) layer includes providing a substrate structure, including a gallium nitride layer, forming a dopant source layer over the gallium nitride layer, and depositing a capping structure over the dopant source layer. The method also includes annealing the substrate structure to diffuse dopants into the gallium nitride layer, removing the capping structure and the dopant source layer, and activating the diffused dopants.

Abstract: An integrated circuit device includes an engineered substrate including a substantially single crystal layer and a buffer layer coupled to the substantially single crystal layer. The integrated circuit device also includes a plurality of semiconductor devices coupled to the buffer layer. The plurality of semiconductor devices can include a first power device coupled to a first portion of the buffer layer and a second power device coupled to a second portion of the buffer layer. The first power device includes a first channel region comprising a first end, a second end, and a first central portion disposed between the first end and the second end. The second power device includes a second channel region comprising a third end, a fourth end, and a second central portion disposed between the third end and the fourth end.

Abstract: An epitaxial semiconductor structure includes an engineered substrate having a substrate coefficient of thermal expansion. The engineered substrate includes a polycrystalline ceramic core, a barrier layer encapsulating the polycrystalline ceramic core, a bonding layer coupled to the barrier layer, and a single crystalline layer coupled to the bonding layer. The epitaxial semiconductor structure also includes an epitaxial layer coupled to the single crystalline layer. The epitaxial layer is characterized by an epitaxial coefficient of thermal expansion substantially equal to the substrate coefficient of thermal expansion.

Abstract: A method for making a multilayered device on an engineered substrate having a substrate coefficient of thermal expansion includes growing a buffer layer on the engineered substrate, and growing a first epitaxial layer on the buffer layer. The first epitaxial layer is characterized by an epitaxial coefficient of thermal expansion substantially equal to the substrate coefficient of thermal expansion.

Abstract: A substrate includes a support structure comprising a polycrystalline ceramic core, a first adhesion layer encapsulating the polycrystalline ceramic core, a barrier layer encapsulating the first adhesion layer, a second adhesion layer coupled to the barrier layer, and a conductive layer coupled to the second adhesion layer. The substrate also includes a bonding layer coupled to the support structure, a substantially single crystal silicon layer coupled to the bonding layer, and an epitaxial semiconductor layer coupled to the substantially single crystal silicon layer.

Abstract: A method of manufacturing a substrate includes forming a support structure by providing a polycrystalline ceramic core, encapsulating the polycrystalline ceramic core in a first adhesion shell, encapsulating the first adhesion shell in a conductive shell, encapsulating the conductive shell in a second adhesion shell, and encapsulating the second adhesion shell in a barrier shell. The method also includes joining a bonding layer to the support structure, joining a substantially single crystalline silicon layer to the bonding layer, forming an epitaxial silicon layer by epitaxial growth on the substantially single crystalline silicon layer, and forming one or more epitaxial III-V layers by epitaxial growth on the epitaxial silicon layer.

Abstract: A method of manufacturing a substrate includes forming a support structure by providing a polycrystalline ceramic core, encapsulating the polycrystalline ceramic core in a first adhesion shell, encapsulating the first adhesion shell in a conductive shell, encapsulating the conductive shell in a second adhesion shell, and encapsulating the second adhesion shell in a barrier shell. The method also includes joining a bonding layer to the support structure, joining a substantially single crystalline silicon layer to the bonding layer, forming an epitaxial silicon layer by epitaxial growth on the substantially single crystalline silicon layer, and forming one or more epitaxial layers by epitaxial growth on the epitaxial silicon layer.

Abstract: A group III-nitride (III-N)-based electronic device includes an engineered substrate, a metalorganic chemical vapor deposition (MOCVD) III-N-based epitaxial layer coupled to the engineered substrate, and a hybrid vapor phase epitaxy (HVPE) III-N-based epitaxial layer coupled to the MOCVD epitaxial layer.