Abstract: An improved power-up circuit for exerting control over output buffer devices in such a way as to disable these buffer devices during the period when the extended circuit is vulnerable to transient effects as the common power supply voltage V.sub.cc is rising during the "power-up" or "power-down" of the extended circuit. One particular such transient effect is the loading down of the power supply due to the buffer devices being in the current-sourcing and in the current-sinking states simultaneously. One improvement over the earlier circuitry is the provision of an asymmetry in the values of V.sub.cc at which control is transferred between the power-up circuit and the rest of the circuit as V.sub.cc is rising during power-up and as V.sub.cc is falling during power-down, respectively. In particular, the design of the present circuit allows control to be exerted over the buffer devices up to a relatively high value of V.sub.

Abstract: A multi-terminal transistor circuit structure is described for TTL applications including current sinking and "pull-down" transistor circuit elements. A transistor pair is coupled with the emitter of the second transistor coupled to the base of the first transistor. The collector and emitter of the first transistor provide first and second terminals and the bases of the transistor pair provide independent third and fourth terminals or current controlled inputs. The new circuit structure is incorporated in a tranistor transistor logic (TTL) output buffer circuit and provides first and second pull-down transistor elements having the emitter of the second transistor coupled to the base of the first pull-down transistor. An independent base drive is coupled to the base of the second pull-down transistor element. The second stage pull-down transistor element introduces full square law enhancement of .beta..sup.

Abstract: A voltage compensated bias generator voltage source includes an all NPN active collector load circuit operatively coupled between the line voltage V.sub.cc and the collector of the shunt regulator transistor of the bias generator. The all NPN active collector load circuit logarithmically reduces variation in shunt regulator transistor collector current with variations in the line voltage V.sub.cc. A transistor of the active collector load circuit also provides in combination with an output transistor of the bias generator a Darlington transistor pair of ECL current source voltage V.sub.cs. A temperature variation countervailing third transistor is also operatively coupled in the active collector load circuit to compensate for temperature variation problems introduced by the active collector load circuit itself.