Abstract: An integrated circuit comprising a reconfigurable arrangement to compute digital algorithms by operating on digital data is provided on an integrated circuit. The integrated circuit includes a plurality of data inputs, a plurality of data outputs, a plurality of programming inputs and a plurality of logic units arranged as a matrix array. At least some of the logic units each comprise a Boolean logic computational unit having input terminals, output terminals, and programming terminals. The logic units are operated on a clocked basis such that each logic unit is controlled by the programming inputs. Each logic unit comprises a selector coupled to the input terminals and programmable to selectively couple input data from either the data inputs or output terminals of one or more other computational units to the computational unit.

Abstract: A programmable integrated circuit for calculating a digital algorithm is disclosed. The integrated circuit is programmable to operate on input data in accordance with one or more predetermined digital algorithms.

Abstract: An integrated circuit comprising a reconfigurable arrangement to compute digital algorithms by operating on digital data is described.

Abstract: A programmable integrated circuit for calculating a digital algorithm is disclosed. The integrated circuit is programmable to operate on input data in accordance with one or more predetermined digital algorithms.

Abstract: A customizable integrated circuit is programmed to provide both hardware task functions and interconnects. A plurality of execution units is executable concurrently to emulate hardware tasks. A plurality of programmable locations provides logical interconnect between the executable programs.