Abstract: Dynamic tag compare circuits employing P-type Field-Effect Transistor (PFET)-dominant evaluation circuits for reduced evaluation time, and thus increased circuit performance, are provided. A dynamic tag compare circuit may be used or provided as part of searchable memory, such as a register file or content-addressable memory (CAM), as non-limiting examples. The dynamic tag compare circuit includes one or more PFET-dominant evaluation circuits comprised of one or more PFETs used as logic to perform a compare logic function. The PFET-dominant evaluation circuits are configured to receive and compare input search data to a tag(s) (e.g., addresses or data) contained in a searchable memory to determine if the input search data is contained in the memory. The PFET-dominant evaluation circuits are configured to control the voltage/value on a dynamic node in the dynamic tag compare circuit based on the evaluation of whether the received input search data is contained in the searchable memory.

Abstract: A device for processing three-dimensional (3D) video data may determine, based on direct dependent layers signaled in a video parameter set, that the current texture layer of the video data is dependent on a depth layer of the video data; and process the current texture layer using the depth layer.

Abstract: This disclosure describes techniques for coding video data according to an intra Block Copy (BC) coding mode. A block vector difference that identifies a prediction block may be represented by a plurality of syntax elements, which may be encoded and decoded. This disclosure proposes various techniques whereby a video encoder may conditionally signal syntax elements representing the absolute value and/or sign of the components of the block vector difference. Likewise, a video decoder may be configured to infer the values of the syntax elements representing the absolute value and/or sign of the components of the block vector difference when such syntax elements are not signaled.

Abstract: In one embodiment, a voltage level shifter includes a first p-type metal-oxide-semiconductor (PMOS) transistor having a gate configured to receive an input signal in a first power domain, and a second PMOS transistor, wherein the first and second PMOS transistors are coupled in series between a supply voltage of a second power domain and a node. The voltage level shifter also includes an inverter having an input coupled to the node and an output coupled to a gate of the second PMOS transistor, and a first n-type metal-oxide-semiconductor (NMOS) transistor having a gate configured to receive the input signal in the first power domain, wherein the first NMOS transistor is coupled between the node and a ground.

Abstract: An apparatus may include an ultrasonic sensor system and a control system. The control system may be configured for controlling the ultrasonic sensor system to obtain first ultrasonic data from at least a part of a target object proximate a surface of the apparatus. The control system may be configured for receiving the first ultrasonic data from the ultrasonic sensor system and for identifying one or more fingerprint ridge features and one or more fingerprint valley features corresponding to the first ultrasonic data. The control system may be configured for determining, based on the first ultrasonic data, one or more fingerprint valley time intervals corresponding to a depth of one or more fingerprint valley features and for performing a spoof detection process based, at least in part, on the one or more fingerprint valley time intervals.

Abstract: In general, the disclosure describes a video coding device (e.g., a video encoder or a video decoder) configured to perform various transformations on video data. The video coding device applies a primary transform to a block of the video data, the primary transform having a first size, and the sub-block being at least a portion of the block. The video coding device determines whether application of a secondary transform, having a second size, to a sub-block of the block is allowed. Application of the secondary transform is disallowed when the first size is equal to the second size. Based on the application of the secondary transform being allowed, the video coding device applies the secondary transform to the sub-block. Application of the primary transform and the secondary transform construct a residual block in a pixel domain.

Abstract: The various aspects provide methods, systems, and devices for coordinating the operating states of multiple SOCs within a computing device. Such coordination may be implemented through communication of information by the SOCs that represent advance notice of impending interactions between each other. The communicated information may be used by a recipient SOC for setting its operating state in advance of the potential impending interaction with another SOC. Accordingly, this technical improvement enables individual SOCs to preemptively influence the operating states of the other SOCs. For example, in the context of power management, the various aspects may coordinate the power states of multiple SOCs, thereby effectively implementing a monolithic power management state machine that improves overall power consumption of the computing device.

Abstract: In an example, a method of decoding video data may include receiving a palette mode encoded block of video data of a picture. The method may include receiving encoded palette mode information for the palette mode encoded block of video data. The encoded palette mode information may include a plurality of instances of a first syntax element and a plurality of syntax elements that are different from the first syntax element. The method may include decoding, using bypass mode, the plurality of instances of the first syntax element before decoding the plurality of syntax elements that are different from the first syntax element using context mode. The method may include decoding, using context mode, the plurality of syntax elements that are different from the first syntax element after decoding the plurality of instances of the first syntax element using bypass mode.

Abstract: A method, an apparatus, and a computer program product for wireless communication are provided. The apparatus may determine that a voice over long term evolution (VoLTE) service has encountered a threshold quantity of failures within a particular period of time. The apparatus may transfer from a VoLTE mode associated with the VoLTE service to another mode for a voice call based on determining that the VoLTE service has encountered the threshold quantity of failures within the particular period of time.

Abstract: Provided are apparatus and methods for ranging between a plurality of wireless devices. An exemplary method includes, at a first wireless device, transmitting a primary portion symbol comprising a first packet and transmitting a secondary portion symbol. The secondary portion symbol is transmitted simultaneously at a lower transmit power than the primary portion symbol, and the secondary portion symbol comprises a second packet identical to the first packet. The primary portion symbol can be transmitted in a first channel having a substantially 20 MHZ bandwidth and the secondary portion can be transmitted in a second channel having a substantially 20 MHZ bandwidth. The first and second channels are substantially adjacent in frequency. After transmitting the primary portion symbol, for example, a high-throughput long-training-field symbol or a very-high-throughput long-training-field symbol can be repetitively transmitted.

Abstract: Leakage-aware activation control of a delayed keeper circuit for a dynamic read operation in a memory bit cell is disclosed. In one aspect, a leakage-aware activation control circuit is provided for a dynamic read circuit configured to perform read operations on a memory bit cell. To prevent or mitigate contention between the delayed keeper circuit and a read port circuit in the dynamic read circuit pulling a dynamic node to opposite voltage levels when a read operation is initiated, the leakage-aware activation control circuit is configured to adaptively control activation timing of the delayed keeper circuit based on a comparison of N-type Field-Effect Transistor (NFET) leakage current to P-type FET (PFET) leakage current. In this manner, the leakage-aware activation control circuit can adaptively adjust the activation timing of the delayed keeper circuit based on the actual relative strengths of NFETs and PFETs.

Abstract: Methods, systems, and devices enable recovery of words spoken while a communication device is on mute during a voice call. A processor of the communication device or a network server may buffer audio segment in memory when the mute function is turned on. If the mute function is turned off soon after the input audio segment begins, or the processor recognizes from the spoken words that the speaker does not intend to be on mute, the processor may transmit to the third party participant a playback of at least one portion of the buffer in conjunction with turning off the mute function. Playback of the buffered audio segment may be sped up so that the playback catches up to current speech of the speaker. Buffering and playback of an input audio segment may be accomplished at the speaker's communication device or in a server within the communication network.

Abstract: Devices and methods to reduce parasitic capacitance are disclosed. A device may include a dielectric layer. The device may include first and second conductive structures and an etch stop layer proximate to the dielectric layer. The etch stop layer may define first and second openings proximate to a region of the dielectric layer between the first and second conductive structures. The device may include first and second airgaps within the region. The device may include a layer of material proximate to (e.g., on, above, or over) the etch stop layer. The layer of material proximate to the etch stop layer may cover the first and second airgaps.

Abstract: Techniques are provided that may be implemented in a mobile device to provide one or more location parameters to one or more mobile processes (e.g., applications) provided and/or otherwise supported, at least in part, by the mobile device. For example, a mobile device may be configured to monitor one or more processes hosted on a first processor, and initiate a communication on a bus connecting the first processor to a positioning engine external to the first processor to obtain at least one updated location parameter in response to detection of activity of at least one of the one or more processes. In certain instances, the updated location parameter(s) may have been previously determined by the positioning engine.

Abstract: This disclosure provides systems, methods and apparatus, including computer programs encoded on computer storage media, for load balancing network traffic in a wireless network. In one aspect, an access point may determine a plurality of client devices that are associated with an overloaded channel of the wireless network. The access point may identify a first client device of the plurality of client devices based, at least in part, on an airtime consumed on the overloaded channel. The access point may determine one or more alternate paths between the access point and the first client device. The access point may forecast airtime to be used by the first client device on channels of the one or more alternate paths, and steer wireless network traffic of the first client device to a first alternate path of the one or more alternate paths based, at least in part, on the forecasted airtime.

Abstract: Certain aspects relate to systems and techniques for submicron alignment in wafer optics. One disclosed method of alignment between wafers to produce an integrated lens stack employs a beam splitter (that is, a 50% transparent mirror) that reflects the alignment mark of the top wafer when the microscope objective is focused on the alignment mark of the bottom wafer. Another disclosed method of alignment between wafers to produce an integrated lens stack implements complementary patterns that can produce a Moiré effect when misaligned in order to aid in visually determining proper alignment between the wafers. In some embodiments, the methods can be combined to increase precision.

Abstract: In an aspect of the disclosure, a method and an apparatus are provided. The apparatus is a register array including first and second flip-flop latch arrays. The first flip-flop latch array includes a first set of master latches, a first set of slave latches coupled to the first set of master latches, and a first address port. The second flip-flop latch array includes a second set of master latches, a second set of slave latches coupled to the second set of master latches, and a second address port. The register array includes an address counter, coupled to the first flip-flop latch array and the second flip-flop latch array. The address counter is shared by the first flip-flop latch array and the second flip-flop latch array and configured to address, in parallel in a test mode, the first flip-flop latch array through the first address port and the second flip-flop latch array through the second address port.

Abstract: Methods, systems, and devices are described for hierarchical modulation and interference cancellation in wireless communications systems. Various deployment scenarios may be supported that may provide communications on both a base modulation layer as well as in an enhancement modulation layer that is modulated on the base modulation layer, thus providing concurrent data streams that may be provided to the same or different user equipments. Various interference mitigation techniques may be implemented in examples to compensate for interfering signals received from within a cell, compensate for interfering signals received from other cell(s), and/or compensate for interfering signals received from other radios that may operate in adjacent wireless communications network.

Abstract: A latch circuit includes an AND-NOR gate, a NAND gate, and a NOR gate. The AND-NOR gate includes a first AND-input configured to receive input data and a second AND-input coupled to an output of the NAND gate. The AND-NOR gate includes a NOR-input coupled to an output of the NOR gate, and an output configured to generate output data. The NAND gate includes a first input coupled to the output of the AND-NOR gate and a second input configured to receive a clock signal. The NOR gate includes a first input coupled to the output of the AND-NOR gate and a second input configured to receive a complementary clock signal. During a first half clock cycle, the AND-NOR gate passes the data from the input to the output. During a second half clock cycle, the feedback configuration of the AND-NOR gate and the NOR gate latches the data.

Abstract: Aspects described herein relate to obtaining provisioned credentials for wireless network services. It can be determined that credentials have not been configured for accessing a network. In this case, a provisioning server supported by the network for obtaining credentials is selected, and a request to establish a connection with the network is transmitted. The transmitted request can indicate the provisioning server.