Abstract: A method for designing an integrated circuit die having bi-directional I/O buffers shared by multiple designs therein. The multi-design integrated circuit die is designed by combining netlists, each of which represents a complete design, and pin-pad assignment lists for the individual designs into a top-level consolidated netlist or multi-design netlist with its own consolidated pin-pad assignment. Data for the top-level consolidated design, including stimulus vectors and response vectors, are used to generate a semiconductor test program to test the integrated circuit die. Consolidation of netlist, pin-pad assignments and vectors are accomplished using design automation software and techniques. The top-level consolidated design data may include configuration information externally applied to the consolidated design.