Abstract: A discrete time filter network with an input signal connection and an output signal connection and comprising a capacitor bank with a plurality of history capacitors, and at least one sampling capacitor which operates at a predetermined cycling rate to couple to at least one history capacitor at a time, which history capacitor is selected from the capacitor bank so as to share electrical charge between such selected history capacitor and the sampling capacitor, wherein there is a plurality of sampling capacitors that are provided in the capacitor bank, and the discrete time filter network is provided with at least one switch network comprising a plurality of clock driven switches for making selected cyclical connections between the sampling capacitors and the history capacitors in the capacitor bank at the predetermined cycling rate.

Abstract: A level shifter (100) is presented comprising an input branch (102) and an output branch (104). The input branch comprises a first switch (130), a voltage clamping unit (120) and a controllable current source (110) in series. The output branch (104) comprises a second switch (140) and a third switch (150) in series, the second switch (140) and third switch (150) having opposite polarities. An output (OUT, 160) is provided between the second and the third switch (140, 150). The current source (110) is controlled by an input signal (IN) and the output signal (OUT). The first switch (130) is controlled by the input signal (IN). Switching control terminals (122, 124) of the second and the third switch are connected on either side of the clamping unit (120). This reduces voltage swing of switching control units, thus resulting in fast switching, less power consumption and wider voltage ranges.