Abstract: A read signal and write signal for a FIFO each has a flag generating edge and a preceding edge. The read or write counter in an empty of full flag generator responds to the preceding edge of the read or write signal so that the empty or full comparator of the generator may generate an updated empty or full flag value before the onset of the flag generating edge. The empty or full flag generator also includes a gate and a pulse generating circuit. The pulse generating circuit responds to the flag generating edge by generating an enabling signal enabling the gate to pass the comparator output to a latch. When the empty or full comparator indicates that a FIFO is empty or full, the comparator output passed by the gate will force the output high, thereby asserting an empty flag or a full flag. The empty flag generator also includes a second pulse generating circuit which updates the empty flag signal to indicate a non-empty FIFO in response to each write signal.

Abstract: A metal silicide layer in or on a body of silicon wafer is used for interconnecting two or more CMOS circuit devices. In addition to a polysilicon layer and a metal layer, the metal silicide layer provides an additional layer of local interconnect which can be performed at high density to reduce the size of the die while including the same number of circuit devices. An amorphous silicon layer doped at selected regions may be used as an additional interconnect.

Abstract: To reduce the access time of a FIFO, a storage device is provided for storing pre-loaded data to be read from the memory array of the FIFO. Thus during each read operation, the pre-loaded data in the storage device is read and the next unit of data to be read during the next read operation is pre-loaded from the array into the storage device. A second storage device is provided for storing the first unit of data written into the array after the array is empty. Thus during the first read operation after the array is rendered non-empty by one or more consecutive write operations, the first unit of data stored in the second storage device is read during the first read operation. This avoids reading garbage from the first storage device which is pre-loaded during the last read operation before the FIFO is empty.

Abstract: A metal silicide layer in or on a body of silicon wafer is used for interconnecting two or more CMOS circuit devices. In addition to a polysilicon layer and a metal layer, the metal silicide layer provides an additional layer of local interconnect which can be performed at high density to reduce the size of the die while including the same number of circuit devices. An amorphous silicon layer doped at selected regions may be used as an additional interconnect.