Patents Assigned to Qualtec Co., Ltd.
  • Publication number: 20260211026
    Abstract: In power-transistor test apparatuses, changing wiring connections to correspond to test items necessitates protracted time. Another issue has been that because connection changing necessitates space for the job, the test apparatuses have become large-scale. To address these issues, disclosed power-transistor test apparatus implementations are furnished with switch-circuit boards on which a conductor plate and a switch circuit are mounted. Plural switch-circuit boards are arranged in parallel, with the conductor plate on each switch-circuit board having a section that juts out beyond the board. Wiring connects the element terminals of an under-test power transistor to the jutting section of the conductor plate of a chosen switch-circuit board. Switching on the switch circuit of the chosen switch-circuit board supplies a test current from a power supply to the under-test power transistor, whereby a power-cycle test is carried out.
    Type: Application
    Filed: March 16, 2026
    Publication date: July 23, 2026
    Applicant: Qualtec Co., Ltd.
    Inventors: Shigeo Sakata, Takahiro Kajinishi, Seiichiro Kihara, Hiroshi Takahara
  • Patent number: 12601776
    Abstract: Power semiconductor-device test apparatuses carrying out gate-signal controlled on/off switching of high-amp test current for various forms of device lifespan testing. Fork plugs or like connectors are insertable through openings of choice in walls partitioning the test apparatus interior for connection, in lieu of altering of wire-line changes, to switch circuits of choice, facilitating test-type connection changing. Sample-connection circuits, removable by means of connectors, include gate-driver, variable-resistor, constant-current, and voltage-output circuits, and via the gate driver circuits generate gate signals, adjustable via the variable-resistor circuits, shorting-circuit on/off applied to the gate terminals of devices under test. The constant-current circuit feeds a diode across the non-gate terminals of a device under test. A control circuit varies current, gate, and output voltages to set the test conditions so that device-under-test temperature will be a predetermined value.
    Type: Grant
    Filed: May 24, 2024
    Date of Patent: April 14, 2026
    Assignee: Qualtec Co., Ltd.
    Inventors: Shigeo Sakata, Takahiro Kajinishi, Seiichiro Kihara, Hiroshi Takahara
  • Publication number: 20250290966
    Abstract: Power semiconductor test apparatuses carrying out gate-signal controlled on/off switching of high-amp test current for various forms of device lifespan testing. Fork plugs or like connectors are insertable through openings of choice in walls partitioning the test apparatus interior for connection, in lieu of altering of wire-line changes, to switch circuits of choice, facilitating test-type connection changing. Sample-connection circuits, removable by means of connectors, include gate-driver, variable-resistor, constant-current, and voltage-output circuits, and via the gate driver circuits generate gate signals, adjustable via the variable-resistor circuits, shorting-circuit on/off applied to the gate terminals of devices under test. The constant-current circuit feeds a diode across the non-gate terminals of a device under test. A control circuit varies current, gate, and output voltages to set the test conditions so that device-under-test temperature will be a predetermined value.
    Type: Application
    Filed: June 1, 2025
    Publication date: September 18, 2025
    Applicant: Qualtec Co., Ltd.
    Inventors: Shigeo Sakata, Takahiro Kajinishi, Seiichiro Kihara, Hiroshi Takahara
  • Publication number: 20240310426
    Abstract: Power semiconductor-device test apparatuses carrying out gate-signal controlled on/off switching of high-amp test current for various forms of device lifespan testing. Fork plugs or like connectors are insertable through openings of choice in walls partitioning the test apparatus interior for connection, in lieu of altering of wire-line changes, to switch circuits of choice, facilitating test-type connection changing. Sample-connection circuits, removable by means of connectors, include gate-driver, variable-resistor, constant-current, and voltage-output circuits, and via the gate driver circuits generate gate signals, adjustable via the variable-resistor circuits, shorting-circuit on/off applied to the gate terminals of devices under test. The constant-current circuit feeds a diode across the non-gate terminals of a device under test. A control circuit varies current, gate, and output voltages to set the test conditions so that device-under-test temperature will be a predetermined value.
    Type: Application
    Filed: May 24, 2024
    Publication date: September 19, 2024
    Applicant: Qualtec Co., Ltd.
    Inventors: Shigeo Sakata, Takahiro Kajinishi, Seiichiro Kihara, Hiroshi Takahara
  • Patent number: 12016229
    Abstract: In EL display panels fabricated by vapor deposition, a vapor-deposition fine mask is employed to form red, green, and blue pixels. An issue, however, has been that misregistration of the vapor-deposition fine mask occurs, lowering manufacturing yields. To resolve this issue, on a thin-film transistor (TFT) substrate, red, green, and blue pixel electrodes are fashioned in matrix form. The TFT substrate is conveyed into a vapor-deposition chamber. Under a vacuum, an organic evaporation source is employed to codeposit a light-emitting layer composed of a host material and a red guest material on the TFT substrate display screen. An ultraviolet laser beam generated by a laser device is optically guided into the vapor-deposition chamber through a laser window and directed on the light-emitting layer formed onto the green and blue pixel electrodes. Positional selecting on the green and blue pixels is carried out by controlling a mirror galvanometer.
    Type: Grant
    Filed: December 8, 2021
    Date of Patent: June 18, 2024
    Assignee: Qualtec Co., Ltd.
    Inventors: Hiroshi Takahara, Yuki Nagata
  • Patent number: 11994551
    Abstract: In this testing device, a space in which a transistor 117 is disposed and a space in which a driving circuit for testing is disposed are separated by a partition wall 214. The driving circuit has a plurality of switch circuit boards 201, and a conductive plate 204 for connection is attached to the switch circuit board 201. A fork plug 205e is connected to a collector c terminal of the transistor 117 to be tested, and a fork plug 205c is connected to an emitter e terminal. The insertion of the fork plug 205 into an opening 216 provided in the partition wall 214 allows the connection of the fork plug 205 and the conductive plate 204. By changing the position of the opening 216 for inserting the fork plug 205, the connection to the driving circuit can be changed in accordance with an item to be tested.
    Type: Grant
    Filed: May 25, 2020
    Date of Patent: May 28, 2024
    Assignee: Qualtec Co., Ltd.
    Inventors: Shigeo Sakata, Takahiro Kajinishi, Seiichiro Kihara, Hiroshi Takahara
  • Publication number: 20220334169
    Abstract: In this testing device, a space in which a transistor 117 is disposed and a space in which a driving circuit for testing is disposed are separated by a partition wall 214. The driving circuit has a plurality of switch circuit boards 201, and a conductive plate 204 for connection is attached to the switch circuit board 201. A fork plug 205e is connected to a collector c terminal of the transistor 117 to be tested, and a fork plug 205c is connected to an emitter e terminal. The insertion of the fork plug 205 into an opening 216 provided in the partition wall 214 allows the connection of the fork plug 205 and the conductive plate 204. By changing the position of the opening 216 for inserting the fork plug 205, the connection to the driving circuit can be changed in accordance with an item to be tested.
    Type: Application
    Filed: May 25, 2020
    Publication date: October 20, 2022
    Applicant: Qualtec Co., Ltd.
    Inventors: Shigeo Sakata, Takahiro Kajinishi, Seiichiro Kihara, Hiroshi Takahara
  • Publication number: 20220208872
    Abstract: In EL display panels fabricated by vapor deposition, a vapor-deposition fine mask is employed to form red, green, and blue pixels. An issue, however, has been that misregistration of the vapor-deposition fine mask occurs, lowering manufacturing yields. To resolve this issue, on a thin-film transistor (TFT) substrate, red, green, and blue pixel electrodes are fashioned in matrix form. The TFT substrate is conveyed into a vapor-deposition chamber. Under a vacuum, an organic evaporation source is employed to codeposit a light-emitting layer composed of a host material and a red guest material on the TFT substrate display screen. An ultraviolet laser beam generated by a laser device is optically guided into the vapor-deposition chamber through a laser window and directed on the light-emitting layer formed onto the green and blue pixel electrodes. Positional selecting on the green and blue pixels is carried out by controlling a mirror galvanometer.
    Type: Application
    Filed: December 8, 2021
    Publication date: June 30, 2022
    Applicant: Qualtec Co., Ltd.
    Inventors: Hiroshi Takahara, Yuki Nagata
  • Patent number: 11266025
    Abstract: Provided are an electronic component manufacturing method by which even a platable layer made of a difficult-to-plate material can be easily plated with good adhesion without using a special chemical solution or a photolithography technique, and an electronic component which has a peel strength of 0.1 N/mm or greater as measured by a copper foil peel test. A picosecond laser beam having a pulse duration on the order of a picosecond or a femtosecond laser beam having a pulse duration on the order of a femtosecond is emitted at a surface of a platable layer (2) in order to roughen the surface, a wiring pattern is formed using a mask (13), and a plated part (12) is formed on the surface of the wiring pattern.
    Type: Grant
    Filed: September 19, 2018
    Date of Patent: March 1, 2022
    Assignee: Qualtec Co., Ltd.
    Inventors: Satoshi Oya, Seiichi Kaihara, Hiroshi Atarashi, Hirokazu Shikata
  • Publication number: 20200288577
    Abstract: Provided are an electronic component manufacturing method by which even a platable layer made of a difficult-to-plate material can be easily plated with good adhesion without using a special chemical solution or a photolithography technique, and an electronic component which has a peel strength of 0.1 N/mm or greater as measured by a copper foil peel test. A picosecond laser beam having a pulse duration on the order of a picosecond or a femtosecond laser beam having a pulse duration on the order of a femtosecond is emitted at a surface of a platable layer (2) in order to roughen the surface, a wiring pattern is formed using a mask (13), and a plated part (12) is formed on the surface of the wiring pattern.
    Type: Application
    Filed: September 19, 2018
    Publication date: September 10, 2020
    Applicant: Qualtec Co., Ltd.
    Inventors: Satoshi Oya, Seiichi Kaihara, Hiroshi Atarashi, Hirokazu Shikata
  • Publication number: 20200111846
    Abstract: An EL display panel fabricated by evaporation creates red, green, and blue pixels using a fine deposition mask (251). However, the displacement of the fine deposition mask (251) decreases the manufacturing yield. In the present invention, red, green, and blue pixel electrodes are arranged in a matrix on a TFT substrate (52). The TFT substrate (52) is transferred into a vacuum deposition chamber (56). A light-emitting layer made up of a host material and a red guest material is codeposited on the presentation screen of the TFT substrate using an organic evaporation source (66) in a vacuum. A laser device (58) generates ultraviolet laser light (59) which is guided into the vacuum deposition chamber (56) through a laser window (63) to irradiate a light-emitting layer formed on the green and blue pixel electrodes. The positions of the green and blue pixels are selected by controlling a galvano mirror (62).
    Type: Application
    Filed: March 23, 2018
    Publication date: April 9, 2020
    Applicant: Qualtec Co., Ltd.
    Inventors: Hiroshi Takahara, Yuki Nagata