Abstract: A quantum circuit for a lattice gas automata simulation includes an initialization step performed by setting up, for the quantum circuit, a position register, a channel register and a first ancilla register. To the position register, the channel register and the first ancilla register are applied in a sequential order: (i) a collision step constructed using a first set of multi-controlled gates, a second set of multi-controlled gates, and four CX gates arranged between the first set and the second set, the collision step being applied to the channel register and the first ancilla register; (ii) a mapping step constructed using two Hadamard gates and four multi-controlled SWAP gates, the mapping step being applied to the channel register and the first ancilla register; and (iii) a propagation step being applied to the position register and the first ancilla register.

Abstract: Disclosed is a method for setting up a quantum circuit (300, 400) utilizing a lattice Boltzmann method. An initialization step (302, 402) is performed by setting up for the quantum circuit, a first quantum register (f1), a second quantum register (f2) and at least a first ancilla register (a, a1). The quantum circuit is applied to the first quantum register (f1), the second quantum register (f2) and the first ancilla register (a, a1), wherein the quantum circuit comprises in a sequential order: (i) a collision step (304, 404) constructed using a first set of quantum gates; (ii) a propagation step (306, 406) constructed using a second set of quantum gates; and (iii) a macroscopic variables calculation step (308, 408) constructed using a third set of quantum gates.

Abstract: A method of setting up a quantum circuit for computational basis state shift. For the quantum circuit, a first quantum register, a second quantum register and a first ancilla register are set up. The first quantum register includes four qubits and the second quantum register includes N?4 qubits. To the first quantum register, the second quantum register and the first ancilla register are applied in a sequential order: (i) an initial step including three CX gates and a first X gate; (ii) a first segment including seven multi-controlled gates; (iii) a second segment comprising a first set of CX gates, a second set of CX gates and a cascade of gates arranged between the first set and the second set; and (iv) a third segment comprising two CX gates and a second X gate.